View HT45R2K-A_7012863.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c ht45r2k-b HT45R2K-A revision: 1.20 date: ?a? ?0? 201? ?a? ?0? 201?
rev. 1.20 2 ?a? ?0? 201? rev. 1.20 ? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale table of contents eates eneal eston eleton table lo aa n ssnen t n eston bsolte a atns c c aatests c caatests operational amplifer electrical characteristics instrumentation amplifer electrical characteristics clocking and pipelining .......................................................................................................... 14 program counter C pc .......................................................................................................... 15 stack ...................................................................................................................................... 16 arithmetic and logic unit C alu ............................................................................................ 16 program ? emor? ......................................................................................................... 17 structure ................................................................................................................................. 17 special vectors ...................................................................................................................... 17 look-up table ......................................................................................................................... 18 table program example ......................................................................................................... 19 data ?emor? ................................................................................................................ 20 structure ................................................................................................................................. 20 special purpose data ?emor? .............................................................................................. 22 special function registers ........................................................................................ 22 indirect addressing registers C iar0 ? iar1 .......................................................................... 22 ?emor? pointers C ?p0? ?p1 ............................................................................................... 22 accumulator C acc ................................................................................................................ 2? program counter low register C pcl ................................................................................... 2? bank pointer C bp .................................................................................................................. 24 status register C status ..................................................................................................... 24 s?stem control register s C ctrl0? ctrl1 .......................................................................... 25
rev. 1.20 2 ?a? ?0? 201? rev. 1.20 ? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale oscillator confguration ............................................................................................. 27 external cr?stal/ceramic oscillator C hxt ............................................................................ 28 external rc oscillator C erc ................................................................................................ 28 internal rc oscillator C hirc ................................................................................................ 29 external ?2.768khz cr?stal oscillator C lxt ......................................................................... 29 lxt oscillator low power function ....................................................................................... ?0 internal 12khz oscillator C lirc ............................................................................................ ?0 watchdog timer C wdt .............................................................................................. 30 watchdog timer clock source ............................................................................................... ?0 watchdog timer operation .................................................................................................... ?0 operating modes ......................................................................................................... 34 power d own ?ode ................................................................................................................. ?4 reset and initialisation ............................................................................................... 36 reset functions ..................................................................................................................... ?6 reset initial conditions .......................................................................................................... ?8 input/output ports ....................................................................................................... 41 pull-high resistors ................................................................................................................. 41 port a wake-up ..................................................................................................................... 42 i/o port control registers ...................................................................................................... 42 pin-shared functions ............................................................................................................. 4? i/o pin structures ................................................................................................................... 44 programming considerations ................................................................................................. 45 timer/event counter s ................................................................................................. 45 timer ?ode ............................................................................................................................ 50 event counter ?ode .............................................................................................................. 50 pulse width ?easurement ?ode ........................................................................................... 51 prescaler ................................................................................................................................ 52 buzzer .................................................................................................................................... 52 i/o interfacing ......................................................................................................................... 54 programming considerations ................................................................................................. 54 timer program example ........................................................................................................ 55 vibration sensor amplifer ......................................................................................... 56 touch key module ....................................................................................................... 56 touch ke ? structure ............................................................................................................... 56 touch key register defnition ................................................................................................ 56 touch ke ? operation .............................................................................................................. 62 touch ke ? interrupt s .............................................................................................................. 6? programming considerations ................................................................................................. 6? charge pump and voltage regulator ........................................................................ 63 operation ............................................................................................................................... 6? dual slope a/d converter .......................................................................................... 65 dual slope a nolog digital convertor operation ..................................................................... 67
rev. 1.20 4 ?a? ?0? 201? rev. 1.20 5 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale interrupts ...................................................................................................................... 70 interrupt register ................................................................................................................... 70 interrupt operation ................................................................................................................. 72 interrupt priorit? ...................................................................................................................... 74 external interrupt .................................................................................................................... 74 timer/event counter interrupt ................................................................................................ 75 ?ulti-function interrupt ........................................................................................................... 75 a/d converter i nterrupt .......................................................................................................... 76 touch ke ? interrupt ................................................................................................................ 76 programming considerations ................................................................................................. 76 l cd driver .................................................................................................................... 77 lcd ?emor? .......................................................................................................................... 77 lcd registers ........................................................................................................................ 78 lcd clock .............................................................................................................................. 79 lcd driver output .................................................................................................................. 79 lcd voltage source and biasing ........................................................................................... 80 programming considerations ................................................................................................. 81 confguration options ............................................................................................................ 82 body fat measurement function ............................................................................... 83 sine wave generator ............................................................................................................. 8? amplifer ................................................................................................................................. 85 filter ....................................................................................................................................... 87 application circuits .................................................................................................... 88 instruction set ............................................................................................................. 89 introduction ............................................................................................................................ 89 instruction timing ................................................................................................................... 89 ? oving and transferring data ................................................................................................ 89 arithmetic operations ............................................................................................................. 89 logical and rotate operations ............................................................................................... 89 branches and control transfer .............................................................................................. 90 bit operations ........................................................................................................................ 90 table read operations .......................................................................................................... 90 other operations .................................................................................................................... 90 instruction set summary ............................................................................................ 91 table conventions .................................................................................................................. 91 instruction defnition .................................................................................................. 93 package information ................................................................................................. 103 80-pin lqfp (10mm 10mm) outline dimensions ............................................................. 104
rev. 1.20 4 ?a? ?0? 201? rev. 1.20 5 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale features operating voltage: C f sys = 4mhz: 2.2v~5.5v C f sys = 8mhz: 3.3v~5.5v oscillator types: C external crystal -- hxt C external low speed crystal -- lxt C external rc -- erc C internal high speed rc -- hirc C internal low speed rc -- lirc up to 22 bidirectional i/o lines one external interrupt input shar e d with an i/o lines one 8-bit and two 16-bit programmable timer/event counter s with overfow interrupt a 8-stage prescal e r lcd driver with 248 segments 16k16 program memory 2568 data memory single differential input channel dual slope analog to digital convertor with operational amplifer watchdog timer with regulator power buzzer output halt and wake-up function s to reduce power consumption internal voltage regulator (3.3v) and charge pump internal reference voltage generator (1.5v) 8-level subroutine nesting bit manipulation instruction 16-bit table read instruction up to 0.5 s instruction cycle with 8mhz system clock at v dd = 5v 63 powerful instructions all instructions in 1 or 2 machine cycles low voltage reset function one vibration sensor input four touch-key inputs body fat circuit 80-pin lqfp package
rev. 1.20 6 ?a? ?0? 201? rev. 1.20 7 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale general description the ht45r2k-c is an 8-bit high performance, risc architecture microcontroller device , which with its a/d converter and lcd driver, can directly interface to analog signals and to lcd panels. the device includes a range of other features such as low power consumption, i/o fexibility, timer functions, oscillator options, d ual slope a/d convertor, halt and wake-up functions, watchdog timer , v ibration sensor etc. however as the device includes all the circuitry associated with body fat measurement the device is especially suitable for this specific application area, being able to signifcantly reduce the need for the usual external components. selection table part no. program memory HT45R2K-A 4k 16 ht45r2k-b 8k 16 ht45r2k-c 16k 16 block diagram
?
?
?
??
? ?- ?

?
?
?
? ? ?? ? ? ?
? ? ?

?
rev. 1.20 6 ?a? ?0? 201? rev. 1.20 7 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale p in assignmen t pa 2 / b z b pa 1 / b z pa 0 / vi b pa 7 / r esb n c pc 0 / t mr 1 / seg 0 pc 1 / t mr 2 / seg 1 pc 2 / se g 2 2 3 4 5 8 9 10 11 12 13 14 3 5 3 6 3 7 41 42 43 44 45 46 47 48 15 16 18 19 20 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 1 51 52 53 54 55 56 57 58 59 60 6 1 6 2 6 3 6 4 49 50 pb 0 / tk 1 pb 1 / tk 2 pb 2 / tk 3 pb 3 / tk 4 pb 4 / int th / lb vobgp chpc 2 vochp voreg op 5 p op 5 n dopap chpc 1 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 22 seg 23 com 7 / seg 24 com 6 / seg 25 com 5 / seg 26 seg 21 com 3 c o m2 c o m1 c 1 c 2 si n f vl f i l r f 1 f vr t o c p0 n r f c d sc c d sr c f i r d sr r vss vd d ht 45 r 2 k - c 80 lqfp - a avss 6 7 pb 5 / tmr 0 avdd 17 r f 2 3 8 3 9 4 0 seg 11 seg 12 seg 10 seg 9 seg 8 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 c o m0 vc va b dchop pa 3 / xt 2 dopan dopao com 4 / seg 27 pc 3 / se g 3 pc 4 / se g 4 pc 5 / se g 5 pc 6 / se g 6 pc 7 / se g 7 pa 4 / xt 1 pa 5 / o sc 2 pa 6 / o sc 1 p in description p in name function opt i/t o/t description pa0/ vib pa0 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. vib vibrc vibration input pa1/ bz pa1 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. bz sfs c?os buzzer output pa2/ bzb pa2 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up bzb sfs c?os complementar? buzzer output pa ?/ xt2 pa ? papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. xt2 co lxt lxt pin pa4/ xt1 pa4 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. xt1 co lxt lxt pin
rev. 1.20 8 ?a? ?0? 201? rev. 1.20 9 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale p in name function opt i/t o/t description pa5/ osc2 pa5 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. osc2 co hxt hxt pin pa6/ osc1 pa6 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. osc1 co hxt hxt/erc pin pa7/ res pa7 pawk st n ?os general purpose i/o. register enabled wake-up. res co st reset input pb0 /tk 1 pb0 pbpu st c?os general purpose i/o. register enabled pull-up. tk1 tk?0c1 touch ke ? 1 in put pb1/ tk2 pb1 pbpu st c?os general purpose i/o. register enabled pull-up. tk2 tk?0c1 touch ke ? 2 in put pb2/ tk? pb2 pbpu st c?os general purpose i/o. register enabled pull-up. tk? tk?0c1 touch ke ? ? in put pb?/ tk4 pb? pbpu st c?os general purpose i/o. register enabled pull-up. tk4 tk?0c1 touch ke ? 4 in put pb4/ int pb4 pbpu st c?os general purpose i/o. register enabled pull-up. int ctrl1 intc0 st external interrupt input pb5/ t?r0 pb5 pbpu st c?os general purpose i/o. register enabled pull-up. t?r0 t?r0c st external timer 0 clock input p c0 / t?r 1/ seg0 p c0 p c pu st c?os general purpose i/o. register enabled pull-up. t?r 1 t?r1c st external timer 1 clock input seg0 lcdout c?os lcd segment output p c1 / t?r 2/ seg1 p c1 p c pu st c?os general purpose i/o. register enabled pull-up. t?r 2 t?r2c st external timer 2 clock input seg1 lcdout c?os lcd segment output p c2 / seg2 p c2 p c pu st c?os general purpose i/o. register enabled pull-up. seg2 lcdout c?os lcd segment output p c? / seg? p c? p c pu st c?os general purpose i/o. register enabled pull-up. seg? lcdout c?os lcd segment output p c4 / seg4 p c4 p c pu st c?os general purpose i/o. register enabled pull-up. seg4 lcdout c?os lcd segment output p c5 / seg5 p c 5 p c pu st c?os general purpose i/o. register enabled pull-up. seg5 lcdout c?os lcd segment output p c6 / seg6 p c6 p c pu st c?os general purpose i/o. register enabled pull-up. seg6 lcdout c?os lcd segment output p c7 / seg7 p c7 p c pu st c?os general purpose i/o. register enabled pull-up. seg7 lcdout c?os lcd segment output seg8~seg2? segn c?os lcd segment outputs co?0~co?? co?n c?os lcd common outputs co?4 / seg27 co?4 lcdc c?os lcd common output seg27 lcd segment output
rev. 1.20 8 ?a? ?0? 201? rev. 1.20 9 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale p in name function opt i/t o/t description co?5 / seg26 co?5 lcdc c?os lcd common output seg26 lcd segment output co?6 / seg25 co?6 lcdc c?os lcd common output seg25 lcd segment output co?7 / seg24 co?7 lcdc c?os lcd common output seg24 lcd segment output vab vab ns lcd voltage pump vc vc ns lcd voltage pump c1 c1 ns lcd voltage pump c2 c2 ns lcd voltage pump vobgp vobgp band gap voltage output pin (for internal use) voreg voreg pwr regulator output ?.?v vochp vochp pwr charge pump output chpc1 chpc1 ns charge pump capacit or C positive chpc2 chpc2 ns charge pump capacit or C negative dopan dopan ns opa negative input dopap dopap ns opa positive input dopao dopao ns opa output dchop dchop ns opa chopper pin th/lb th ns temperature sensor input lb ns low batter? voltage input dsrr dsrr ns r eference signal input dsrc dsrc ns integrator negative input dscc dscc ns c omparator negative input sin sin ns sine wave output fvr fvr ns foot resistor channel fvl fvl ns foot resistor channel fil fil ns foot resistor channel fir fir ns foot resistor channel rf1 rf1 ns reference impedance channel rf2 rf2 ns reference impedance channel rfc rfc adc analog input t0 t0 opac output cp0n cp0n ns the inverting input of cp0 op5n op5n ns the inverting input of op5 op5p op5p ns the non-inverting input of op5 v dd v dd pwr p ower suppl? v ss v ss pwr ground a vdd a vdd pwr analog power suppl? a vss a vss pwr analog g round note : i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; cmos: cmos output; nmos: nmos output hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator ns: non-standard input or output
rev. 1.20 10 ?a? ?0? 201? rev. 1.20 11 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale absolute maximum ratings supply voltage ..................................................................................................... v ss -0.3v to +6.0v input voltage ................................................................................................. v ss -0.3v to v dd +0.3v storage temperature ................................................................................................ -50 c to +125c operating temperature .............................................................................................. -40 c to +85 c i ol total ................................................................................................................................. 150ma i oh total ................................................................................................................................ -100ma total power dissipation .................................................................................................... 500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. c haracteristics operating temperature: -40c c to 85c ta= 25c t ?pical symbol parameter test conditions min. typ. max. unit vdd conditions v dd operating voltage f sys = 4?hz 2.2 5.5 v f sys = 8?hz ?.? 5.5 v v lcd lcd highest voltage 0 v dd v i dd1 operating current ( hxt ? erc?hirc) 5v no load? f sys = 8? hz adc off 4 8 ma i dd2 operating current ( hxt ? erc?hirc) ?v no load? f sys = 4? hz adc off 0.8 1.5 ma 5v 2.5 4.0 ma i dd? operating current ( hxt ? erc) ?v no load? f sys = 2? hz adc off 0.5 1.0 ma 5v 1.5 ?.0 ma i dd4 operating current (hxt ? erc?hirc) 5v v oreg = ?.?v ? f sys = 4 ?hz adc on ? adc clock is 125 khz (all other analog devices off) ? 5 ma i stb1 standb? current ?v no load? s? stem halt ? adc ? lcd and wdt off 1 a 5v 2 a i stb2 standb? current ?v no load? s? stem halt ? adc and lcd off ? wdt on 2.5 5.0 a 5v 8 15 a i stb? standb? current ( internal rc 12khz ) ?v no load? s? stem osc off? adc and wdt off 2 5 a 5v 6 10 a i s t b4 standb? current ( internal rc 12khz ) 5v no load? s? stem osc off? adc and wdt off lcd on(1/ ? r t?pe) ?80 500 a i stb 5 standb? current ?v no load? s ?stem halt ? lxt osc slowl? start - up ? wdtosc off ? lx t o n 5 a 5 v 15 a i s t b6 standb? current (lxt) 5v no load? s ? stem osc off? adc and wdt off ? lcd on (1/? r t?pe)? (lcd bias current= 50a) ?90 510 a i st b 7 standb? current ?v no load? onl? vibration sensor turn on&vib pin connected a 0.1f cap to vss ? wdt off 2 4 a 5 v 8 16
rev. 1.20 10 ?a? ?0? 201? rev. 1.20 11 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale symbol parameter test conditions min. typ. max. unit vdd conditions v il1 input low voltage for i/o ports ? t?r0? t?r1 ? t?r2 and int 5 v 0.0 1.5 v 0.0 0. 2 v dd v v ih1 input high voltage for i/o ports? t?r0? t?r1 ? t?r2 and int 5 v ?.5 5.0 v 0. 8 v dd 1.0v dd v v il2 input low voltage ( res ) 0 0.4v dd v v ih2 input high voltage ( res ) 0.9v dd v dd v v lv r1 low v oltage reset confguration option: 2.1v 2.0 2.1 2.2 v v lvr2 confguration option: 2.55v 2.40 2.25 2.70 v v lvr ? confguration option: 3.15v ?.00 ?.15 ?.?0 v v lvr4 confguration option: 3.8v ?.6 ?.8 4.0 v i ol1 i/o port sink current ?v v ol = 0.1v dd 4 8 ma 5v 10 20 ma i oh1 i/o port source current ?v v oh = 0.9v dd -2 -4 ma 5v -5 -10 ma i ol2 lcd c ommon and s egment sink current ?v v ol = 0.1v dd 210 420 a 5v ?50 700 a i oh2 lcd c ommon and s egment source current ?v v oh = 0.9v dd -80 -160 a 5v -180 -?60 a i ol ? pa7 s ink c urrent 5 v ol = 0.1v dd 2 ? ma r ph pull-high resistance of i/o ports ?v 20 60 100 k 5v 10 ?0 50 k v vibwk ?inimum v oltage to w ake ?cu b? the v ibration s ensor i nput 2.4 v 100hz~1khz sine wave (note) 250 mv ? v 5 v charge pump and regulator v chp input voltage charge p ump on 2.2 ?.6 v charge p ump off ?.7 5.5 v v oreg output voltage n o load ?.0 ?.? ?.6 v v regdp1 regulator output voltage drop ( c ompare d with n o l oad) v dd = ?.7v ~ 5.5v charge pump off current<= 10ma 100 mv v regdp2 v dd = 2.4v ~ ?.6v charge pump on current <= 6ma 100 mv dual slope ad convertor , amplifer and band gap v adoff input offset range v oreg = ?.?v 500 800 v v rfgtc reference g enerator t emperature c oeffcient v oreg = ?.?v 50 ppm /c v ic? r common ?ode input range amplifer, n o load 0.2 v oreg -1.2 v integrator ? n o load 1.2 v oreg -0.2 v note : test circuit for v vmbwk .
rev. 1.20 12 ?a? ?0? 201? rev. 1.20 1? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale
a.c. characteristics operating temperature: -40c to 85c ta= 25c t ?pical symbol parameter test conditions min. typ. max. unit vdd conditions f sys s?stem clock (rc) 2.2v~5.5v 400 4000 khz s?stem clock ( hxt ) 2.2v~5.5v 400 4000 khz ?.?v~5.5v 400 8000 khz 4.5 v ~5.5v 400 12000 khz f hirc hirc osc ? v /5 v ta= 25c -2% 4 +2% ?hz ? v /5 v ta= 25c -2% 8 +2% ?hz 5 v ta= 25c -2% 12 +2% ?hz ? v /5 v ta= 0~70c -5% 4 +5% ?hz ? v /5 v ta= 0~70c -5% 8 +5% ?hz 5 v ta= 0~70c -5% 12 +5% ?hz 2.2 v ~?.6 v ta= 0~70c -8% 4 +8% ?hz ?.0 v ~5.5 v ta= 0~70c -8% 4 +8% ?hz ?.0 v ~5.5 v ta= 0~70c -8% 8 +8% ?hz 4.5 v ~5.5 v ta= 0~70c -8% 12 +8% ?hz 2.2 v ~?.6 v ta= -40~85c -12% 4 +12% ?hz ?.0 v ~5.5 v ta= -40~85c -12% 4 +12% ?hz ?.0 v ~5.5 v ta= -40~85c -12% 8 +12% ?hz 4.5 v ~5.5 v ta= -40~85c -12% 12 +12% ?hz f erc erc osc 5 v ta= 25c ? r= 120k -2% 4 +2% ?hz 5 v ta= 0~70c ? r= 120k -5% 4 +5% ?hz 5 v ta= -40~85c ? r= 120k -7% 4 +7% ?hz 2.2 v ~5.5 v ta= -40~85c ? r= 120k -11% 4 +11% ?hz f ti?er timer i/p frequenc ? (t?r0?t?r1 ?t?r2 ) 2.2v~5.5v 0 4000 khz t wdtosc watchdog oscillator period ?v 45 90 180 s 5v ?2 65 1?0 s t res external reset low pulse width 1 s t sst s? stem start-up timer period ( wake-up from halt ) 2 1024 t sys t int interrupt pulse width 1 s t lvr low v oltage w idth to r eset 0.25 1.00 2.00 ms note: 1. t sys = 1/f sys 2. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1 f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible.
rev. 1.20 12 ?a? ?0? 201? rev. 1.20 1? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale operational amplifer electrical characteristics symbol parameter test conditions min. typ. max. unit v dd conditions dc electrical characteristics v dd suppl? voltage 2. 2 5.5 v i cc suppl? current per signal amplifer 5v no load 150 ?60 500 a op0, op2 sr slew rate at unit? gain ?v r l = 100k, c l = 100pf 7.5 v/s gbw gain bandwidth product ?v r l = 100k, c l = 100pf 2 ?hz op1 sr slew rate at unit? gain ?v r l = 100k, c l = 100pf 7.5 v/s gbw gain bandwidth product ?v r l = 100k, c l = 100pf 5 ?hz instrumentation amplifer electrical characteristics symbol parameter test conditions min. typ. max. unit v dd condition v dd suppl? voltage 2.2 5.5 v icc suppl? current 5v io= 0a 1.2 ma sr slew rate at unit? gain ?v rl= 100k, cl= 100pf 7.5 v/s gbw gain bandwidth product ?v rl= 100 k, cl= 100pf 5 ?hz ger gain error -10% 10% vos input offset voltage ?v -15 15 mv power-on reset characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd rising rate to ensure power-on reset 0.0?5 v/ms v dcpor_?ax dc por ? aximum voltage 0.6 2.2 v t por 1 ? inimum time for vdd sta?s at vpor to ensure power-on reset without 0.1 m f between vdd and vss 2 s t por 2 ? inimum time for vdd sta?s at vpor to ensure power-on reset with 0.1 m f between vdd and vss 10 s
rev. 1.20 14 ?a? ?0? 201? rev. 1.20 15 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility. clocking and pipelining the system clock, derived from an rc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4.the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ?
rev. 1.20 14 ?a? ?0? 201? rev. 1.20 15 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale
? ? ? ? ?? ? ? - ? ? ? ? ? ? ? ? ? -? program counter C pc during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. i t must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc. the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high b?te pcl register low b?te pc1 ? ~pc8 pcl7~pcl0
the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, which is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section.
rev. 1.20 16 ?a? ?0? 201? rev. 1.20 17 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack.
if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.20 16 ?a? ?0? 201? rev. 1.20 17 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale program m emory the program memory is the location where the user code or program is stored. the device is supplied with one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the fexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. structure the program memory has a capacity of 16k16. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. the device has its program memory divided into two banks, bank 0 and bank 1. the required bank is selected using bit 5 of the bp register.
? ? ? ? ? ? ? ? ?? -? ? ? ?? -? ? ? ? ? program memory structure special vectors within the program memory, certain locations are reserved for special usage such as reset and interrupts. reset vector this vector is reserved for use by the device reset for program initialization. after a device reset is initiated, the program will jump to this location and begin execution. external interrupt vector this vector is used by the external interrupt. if the external interrupt pin on the device receives an edge transition, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. the external interrupt active edge transition type, whether high to low, low to high or both is specifed in the ctrl1 register. timer/event 0/1 counter interrupt vector this internal vector is used by the timer/event 0/1 counters. if a timer/event counter overfow occurs, the program will jump to its respective location and begin execution if the associated timer/ event counter interrupt is enabled and the stack is not full.
rev. 1.20 18 ?a? ?0? 201? rev. 1.20 19 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale multi-function interrupt vector this vector is used by the multi-function interrupt. if t he timer/event 2 counter overfow or touch key 16-bit or 10-bit counter overfow, the program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. a/d convertor interrupt vector this internal vector is used by the a/d convertor interrupt . if the a/d conversion process fnishes, the program will jump to this location and begin execution if the a/d convertor interrupt is enabled and the stack is not full. touch key interrupt vector this internal vector is used by the touch key interrupt . if the counter in the relevant touch key module overfow occurs , the program will jump to this location and begin execution if the touch key interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp. this register defnes the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd c [m] or tabrdl[m] instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.
?
rev. 1.20 18 ?a? ?0? 201? rev. 1.20 19 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 3f00h which refers to the start address of the last page within the 16k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 3f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd c [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd l [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. instruction(s) table location b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc1? pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @? @2 @1 @0 tabrdl [m] 1 1 1 1 1 1 @7 @6 @5 @4 @? @2 @1 @0 table location note: 1. pc13~pc8: current program counter bits 2. @7~@0: table pointer tblp bits 3. b13~b0: table address location bits table read program example tempreg1 db ? ;temporary register #1 tempreg2 db ? ;temporary register #2 : : mov a,06h ;initialise low table pointer - note that this ;address mov tblp,a ;is referenced : : tabrdl tempreg1 ;transfers value in table referenced by table ;pointer data at program ;memory address 3f06h transferred to tempreg1 ;and tblh dec tblp ;reduce value of table pointer by one tabrdl ;tempreg2 ;transfers value in table referenced by table ;pointer data at program ;memory address 3f05h transferred to tempreg2 ;and tblh in this ; example the data 1ah is transferred to tempreg1 ;and data 0fh to register tempreg2 : : org 3f00h ;sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh
rev. 1.20 20 ?a? ?0? 201? rev. 1.20 21 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure the data memory is divided into four banks, bank0~3. the bank0 is subdivided into two sections, the frst of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. the general purpose data memory bank1 and bank2 are dedicated for the lcd and sine pattern functions respectively while the bank3 is used for general purpose data memory. the total capacity of general purpose data memory, available for designer, is 256 bytes, composed by bank0 and bank4. the accompanying table illustrates the data memory arrangement. capacity bank description 256 8 bank 0(00h~?fh) special function data ?emor?( 64b?tes) bank 0(40h~ffh) general purpose data ?emor?(192 b?tes) bank 1(40h~5bh) general purpose data ?emor? for lcd(28 b?tes) bank 2(40h~7fh) general purpose data ?emor? for s ine p attern(64 b?tes) bank ?(40h~7fh) general purpose data ?emor?(64 b?tes) note: the data ram capacity consists of the general purpose data ram in bank0 and bank3, except the bank1 and bank2 which are assigned to the lcd and sine pattern functions. all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user program for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. for this device, the data memory is divided into four banks, which are selected using a bank pointer. only data in bank 0 can be directly addressed, data in bank 1~ 3 must be indirectly addressed.
?? ? ? ?? ?

rev. 1.20 20 ?a? ?0? 201? rev. 1.20 21 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale

??? ? ??? ? ???
? ? ?? special purpose data memory
rev. 1.20 22 ?a? ?0? 201? rev. 1.20 2? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale

?
? ?
? ? ? ? ?? ? ??? general purpose data memory special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h. special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location s of these registers within the data memory begin at the address 00h and are mapped into from bank 0 to bank 3 . any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved and attempting to read data from these locations will return a value of 00h. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory p ointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to indirectly address and track data. mp0 can only be used to indirectly address data in bank 0 while mp1 can be used to address data from bank 0 to bank 3 . when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. note that indirect addressing using mp1 and iar1 must be used to access any data in bank 1~bank 3 . the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4.
rev. 1.20 22 ?a? ?0? 201? rev. 1.20 2? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org00h start mov a 04h ;setup size of block mov block a mov a offset adres1 ;accumulator loaded with frst ram address mov mp0 a ;setup memory pointer with frst ram address loop clr iar0 ;clear the data at address defned by mp0 inc mp0 ;increment memory pointer sdz block ;check if last memory location has been cleared jmp loop continue the important point to note here is that in the example, no reference is made to specific data memory addresses. accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading dydoxhgluhfwolqwrwklv3/uhjlvwhuzloofdxvhdmxpswrwkhvshflhg3urjudp0hpruorfdwlrq however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted.
rev. 1.20 24 ?a? ?0? 201? rev. 1.20 25 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale bank pointer C bp in this device, the program and data memory are divided into several banks. selecting the required program and data memory area is achieved using the bank pointer. bit 5 of the bank pointer is used to select program memory bank 0 or 1, while bits 0~ 1 are used to select data memory banks 0~ 3 . the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using i ndirect addressing. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. bp register bit 7 6 5 4 3 2 1 0 name p?bp0 d?bp1 d?bp0 r/w r/w r/w r/w por 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 pmbp0 : program memory bank pointer 0: bank 0, program memory address is from 0000h ~ 1fffh 1: bank 1, program memory address is from 2000h ~ 3fffh bit 4 ~ 2 unimplemented, read as 0 bit 1 ~ 0 dmbp 1 ~ dmbp0 : data memory bank pointer 00: bank 0 (for general purpose) 01: bank 1 (for lcd) 10: bank 2 (for sine generator) 11: bank 3 (for general purpose) status register C status this 8-bit register contains the zero flag(z), carry flag (c), auxiliary carry flag(ac), overflow flag(ov), power down flag(pdf), and watchdog time-out flag(to). these arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like any other register. any data written into the status register will not change the to and pdf flags. in addition operations related to the status register may give different results from those intended. the to fag can be affected only by system power-up, a wdt time-out or executing the halt or clr wdt instruction. the pdf fag can be affected only by executing the halt or clr wdt instruction or a system power-up. the z, ov, c, ac fags generally refect the statuses of the latest operations. in addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto stack automatically. if the contents of status are important and the subroutine can corrupt the status register, the programmer has to take precautions to save it properly.
rev. 1.20 24 ?a? ?0? 201? rev. 1.20 25 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x" unknown bit 7~6 unimplemented, read as "0" bit 5 to : watchdog time-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction system control register s C ctrl0, ctrl1 these registers are used to provide control o ver various internal functions. some of these include the timer/event counter 2 internal source option , the lcd driver clock (fsub) option, power down mode clock control, certain system clock options, external interrupt edge trigger type, and the 32.768khz crystal oscillator (lxt) enable contr ol. ctrl0 register bit 7 6 5 4 3 2 1 0 name tcks1 tcks0 lfs lcdck1 lcdck0 fsubc fsubs lxtlp r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 1 bit 7 ~6 tcks1~tcks0 : timer/event counter 2 internal source selection 0 0: f l (low frequency clock) 0 1: f ref (reference frequency clock generated from touch key module) 10: f sen (sensor frequency clock generated from touch key module) 11: f tmck (gated sensor frequency clock generated from touch key module) if the touch key module is disabled, the tcks1 and tcks0 bits are always set to 00 and can not be written to.
rev. 1.20 26 ?a? ?0? 201? rev. 1.20 27 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale bit 5 l fs : low frequency clock source f l selection 0: lirc oscillator 1: lxt oscillator bit 4 ~3 lcdck1~lcdck0 : to select the lcd driver clock 00: lcd clock = f sub /3 01: lcd clock = f sub /4 10 : lcd clock = f sub /8 11: lcd clock = f sub /8 bit2 f sub c : f sub power down mode clock control 0: di s abled 1: enabled bit1 fsubs : f sub clock source selection 0: lirc oscillator 1: lxt oscillator bit0 lxtlp : lxt oscillator low power control function 0: lxt oscillator quick start-up mode 1: lxt oscillator low power mode ctrl1 register bit 7 6 5 4 3 2 1 0 name e int c 1 e int c 0 bzcs lxt en r/w r/w r/w r/w r/w por 0 0 0 1 bit 7 ~ 6 eintc 1, eintc 0 : external interrupt edge selection 00: disable 01: falling edge trigger 10: rising edge trigger 11: dual edge trigger bit 5 ~2 unimplemented, read as 0 bit 1 bzcs : buzzer clock source selection 0: from timer/event counter 0 1: from timer/event counter 1 bit 0 lxten : lxt oscillator control in power down mode 0: disabled 1: enabled
rev. 1.20 26 ?a? ?0? 201? rev. 1.20 27 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale oscillator confguration the device provides three system oscillator circuits known as a crystal oscillator (hxt), an external rc oscillator (erc) and an internal high speed rc oscillator (hirc) which are used for the system clock. there are also an internal 12khz rc (lirc) and a 32.768khz crystal oscillator (lxt) which can provide a source clock for the wdt clock named f s , the lcd driver clock, named f sub and the timer/event counters low frequency clock, named f l ,for various timing purposes. erc lxt lirc high frequenc y oscillation ( hosc ) low frequenc y oscillation ( losc ) lfs f l f sys f sys /4 f sub wdt timer fs hirc hxt configuration option ?halt? oscon f sys fsubs lcd ?halt? fsubc prescaler (/3, /4 , /8 ) lcdck [1:0 ] f sys / 4 configuration optio n system clock confgurations in the power down mode, the system oscillator, the internal 12khz rc oscillator (lirc) or the external 32.768khz crystal oscillator (lxt) may be enabled or disabled depending upon the corresponding clock control bit described in the relevant sections. the system can be woken-up from the power down mode by the occurrence of an interrupt, a transition determined by confguration options on any of the port a pins, a wdt overfow or a timer overfow. the accompanying table illustrates the oscillator type list. type name freq. pins external cr?stal hxt 400khz~ 12 ?hz osc1/osc2 external rc erc 400khz~ 12 ?hz osc1 internal high speed rc hirc 4 ? 8 or 12?hz external low speed cr?stal lxt ?2.768khz xt1 / xt2 internal low speed rc lirc 1 2khz oscillator types
rev. 1.20 28 ?a? ?0? 201? rev. 1.20 29 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale external crystal/ceramic oscillator C hxt the external crystal/ceramic system oscillator is one of the system oscillator choices, which is selected via confguration options. for most crystal oscillator confgurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors and resistors. however, if a resonator instead of crystal is connected between osc1 and osc2, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specifcation.

?
? ?? ??

external rc oscillator C erc using the erc oscillator onl? requires that a resistor ? with a value between 24k and 1.5 ? ? is connected between osc1 and vdd ? and a capacitor is connected between osc1 and ground? providing a low cost oscillator configuration. it is onl? the external uhvlvwruwkdwghwhuplqhvwkhrvfloodwlrqiuhtxhqfwkhh[whuqdofdsdflwrukdvqrlqxhqfh over the frequenc? and is connected for stabilit? purposes onl? . device trimming during the manufacturing process and the inclusion of internal frequenc ? compensation circuits are xvhgwrhqvxuhwkdwwkhlqxhqfhriwkhsrzhuvxssoyrowdjhwhpshudwxuhdqgsurfhvv variations on the oscillation frequenc? are minimised. as a resistance/ frequenc? reference point? it can be noted that with an external 120k resistor connected and with a 5v voltage power suppl? and temperature of 25 degrees ? the oscillator will have a frequenc? of 4? hz within a tolerance of 2%. here onl ? the osc1 pin is used? which is shared with i/o pin pa6? leaving pin pa5 free for use as a normal i/o pin external rc oscillator C erc
rev. 1.20 28 ?a? ?0? 201? rev. 1.20 29 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fxed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 2 5 degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pa5 and pa6 are free for use as normal i/o pins. external 32.768khz crystal oscillator C lxt the external 32.768khz crystal oscillator is one of the low frequency oscillator choices, which is selected via a confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the power down mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the power down mode. to do this, another clock, independent of the system clock, must be provided. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. the external parallel feedback resistor, rp, is required.
? ? ? ?? ??-? ? ? ?
lxt oscillator c1 and c2 values crystal frequency c1 c2 ?2768hz 8pf 10pf note: 1. c1 and c2 values are for guida nce onl? . 2. r p 0a0lvuhfrpphqgh d. 32768hz c rystal recommended capacitor values
rev. 1.20 ?0 ?a? ?0? 201? rev. 1.20 ?1 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the ctrl0 register. lxtlp bit lxt mode 0 quick start 1 low-power after power on, the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally; the only difference is that it will take more time to start up if in the low- power mode. internal 12khz oscillator C lirc the internal 12khz rc oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical period of approximately 65us at 5v, requiring no external components for its implementation. if the system enters the power down mode, the internal rc oscillator can still continue to run if its clock is necessary to be used to clock the functions for timing purpose such as the wdt function, lcd driver or timer/event counters. the internal rc oscillator can be disabled only when it is not used as the clock source for all the peripheral functions determined by the confguration options of the wdt function and the relevant control bits which determine the clock is enabled or disabled for related peripheral functions. watchdog timer C wdt the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the wdt is implemented using an internal 12khz rc oscillator known as lirc, the external lxt 32.768khz oscillator or the instruction clock which is the system clock divided by 4. watchdog timer operation the timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. a confguration option determines whether the watchdog timer is to be always on or whether its enable/disable control is und er software control. if the confguration option chooses the always on option, then any we4~we0 values other than 01010 or 10101 will result in an mcu reset being generated. if the confguration option chooses the software control option then the watchdog timer can be disabled by setting the we4~we0 bits to a 10101 value. a value of 01010 will enable the watchdog timer and any other value will generate an mcu reset. the actual reset will be generated after 2~3 lirc clock cycles.
rev. 1.20 ?0 ?a? ?0? 201? rev. 1.20 ?1 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale wdt confg. option we4 ~ we0 bits wdt function always on 01010 enabled 10101 enabled other values ?cu reset generated after 2~? lirc clock c?cles software control 01010 enabled 10101 disabled other values ?cu reset generated after 2~? lirc clock c?cles wdt functional control summary the application can generate a software reset by writing a value other than 01010 and 10101 into the we4~we0 bits. if this is done then the wrf fag in the wdtc1 register will be set. the wdt clock is divided by an internal counter to give a ratio division with a range of 2 8 ~2 15 selected using the ws0~ws2 bits, to give a longer watchdog time-out period. if the watchdog timer is disabled, the wdt timer will not generate a chip reset. so in the watchdog timer disable mode, the wdt timer counter can be read out and can be cleared. this function is used for the application program to access the wdt frequency to get the temperature coeffcient for analog component adjustment. the lirc oscillator can be disabled or enabled by the oscillator enable control bits lircen1 and lircen0 in the wdt control register wdtc for power saving reasons . there are three registers related to the wdt function named wdtc, wdtc1 and wdtd. the wdtc and wdtc1 registers control the wdt oscillator enable/disable and the wdt power source. the wdtd register is the wdt counter content register and is read only. the wdt power source selection bits named lircpwr1 and lircpwr0 are used to choose the wdt power source. the wdt default power source is from vochp. the main purpose of the regulator is to be used for wdt temperature-coeffcient adjustment. in this case, the application program should enable the regulator before switching to the regulator source. the lircen1 and lircen0 bits can be used to enable or disable the lirc oscillator. if the application does not use the lirc oscillator, then it needs to disable it in order to save power. when the lirc oscillator is disabled, then it is actually turned off, regardless of the setting of the relevant control bits which select the lirc oscillator as its clock source. when the lirc oscillator is enabled, it can be used as the clock source in the power down mode defined by the corresponding control bits of the peripheral functions. the wdt clock source may also come from the instruction clock, in which case the wdt will operate in the same manner except that in the power down mode the wdt may stop counting and lose its protecting purpose. if the device operates in a noisy environment, using the on-chip lirc oscillator is strongly recommended, since the halt instruction will stop the system clock. when the wdt overfows under normal operation a device reset will be executed and the status bit to will be set. in the power down mode, the overfow executes a warm reset, here only the pc and sp bits are reset to zero. there are three methods to clear the contents of the wdt, an external reset - a low level on res -, a software instruction or a halt instruction. there are two types of software instructions; the single clr wdt instruction, or the pair of instructions, clr wdt1 and clr wdt2. of these two types of instruction, only one type of instruction can be active at a time depending on the confguration option C clr wdt times selection option. if the clr wdt is selected (i.e., clr wdt times equal one), any execution of the clr wdt instruction clears the wdt. if the clr wdt1 and clr wdt2 option is chosen (i.e., clr wdt times equal two), these two instructions have to be executed to clear the wdt, otherwise the wdt may reset the device due to a time-out.
rev. 1.20 ?2 ?a? ?0? 201? rev. 1.20 ?? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale

?
??
? ? ? ?- ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ? - ? ? ? ? ? watchdog timer wdtc register bit 7 6 5 4 3 2 1 0 name ws2 ws1 ws0 lircen1 lircen0 lircpwr1 lircpwr0 r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 s s 0 1 bit 7~5 ws2~ws0 : wdt prescaler rate select 000: 2 8 /f s 001: 2 9 /f s 010: 2 10 /f s 011: 2 11 /f s 100: 2 12 /f s 101: 2 13 /f s 110: 2 14 /f s 111: 2 15 /f s bit 4 unimplemented, read as "0" bit 3~2 lircen1 ~ lircen0 : lirc oscillator enable/disable control bits 00: lirc oscillator is enabled 01: lirc oscillator is disabled 10: lirc oscillator is enabled 11: lirc oscillator is enabled it is strongly recommended to use 10 for wdt osc enable bit 1~0 lircpwr1 ~ lircpwr0 : lirc power source select 00: wdt power comes from vochp 01: wdt power comes from vochp 10: wdt power comes from regulator 11: wdt power comes from vochp it is strongly recommended to use 01 for vochp to prevent the noise to let the wdt lose the power the wdt clock (f s ) is further divided by an internal counter to give longer watchdog time-out period. in this device, the division ratio can be varied by selecting different values of ws2~ws0 bits to give 2 8 /f s to 2 15 /f s division ratio range.
rev. 1.20 ?2 ?a? ?0? 201? rev. 1.20 ?? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale wdtc1 register bit 7 6 5 4 3 2 1 0 name we4 we? we2 we1 we0 lvrf lrf wrf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 x 0 0 bit 7 ~ 3 we4~we0 : wdt enable/disable/mcu reset control 01010b: enable C power on value 10101b: function depends upon wdt confguration option. for the wdt always on option this value will enable the wdt. for the software control option this value will disable the wdt. other values: generates mcu reset after 2~3 lirc clock cycles. bit 2 lvrf : lvrf reset fag 0: lvr not active 1: lvr active this bit can be cleared to 0 by the application program, but can not be set to 1. bit 1 lrf : reset caused by lvrc setting 0: not active 1: active this bit can be cleared to 0 by the application program, but can not be set to 1. bit 0 wrf : reset generated by we4~we0 bits wdtd register bit 7 6 5 4 3 2 1 0 name wdtd7 wdtd6 wdtd5 wdtd4 wdtd? wdtd2 wdtd1 wdtd0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 w dtd7 ~ w dtd 0 : wdt counter value (bit 4~bit 11) this register is read only and used for temperature adjusting
rev. 1.20 ?4 ?a? ?0? 201? rev. 1.20 ?5 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale operating modes the device has two operational modes, the normal mode and the power down mode. in the normal mode, the high speed system clock may come from external rc (erc), external crystal (hxt) or internal rc (hirc) oscillator. when in the power down mode, the clocks in this device are all enabled or disabled using software. the accompanying table illustrates the operating modes and system clock control. operating mode control halt instruction mode system oscillator fsubc f sub clock lxt en lxt oscillator (xt1/xt2) not executed normal on x enable x on executed power down on(oscon=1) off(oscon=0) 0 disable 1 on power down on(oscon=1) off(oscon=0) 1 enable 1 on power down on(oscon=1) off(oscon=0) 0 disable 0 off power down on(oscon=1) off(oscon=0) 1 enable 0 off note: the lircen1 and lircen0 bits in the wdtc register can be setup to enable the lirc. if the lvr is enabled, then the lirc will also be enabled. however, as the lirc is powered by the internal voltage regulator, which is controlled by the regen bit in the chprc register, then when the regen bit is cleared to zero, the lirc and the lvr will both be disabled. therefore, the regen bit should be set 1 to enable these two functions. refer to the wdt section for the details regarding the wdtosc setup. power d own mode the power down mode is initialised by the halt instruction and results in the following. the system oscillator stops running if the system oscillator is selected to be turned off by clearing the oscon bit in the haltc register to zero. otherwise, the system oscillator will keep running if it is selected to be turned on in the power down mode. the contents of the data memory and of the registers remain unchanged. the wdt is cleared and starts recounting if the wdt clock source is from the lirc or the lxt oscillator. all i/o ports maintain their original status. the pdf fag is set but the to fag is cleared. the lcd driver keeps running if the lcd clock f sub is enabled by setting the fsubc bit high and the lcdon bit in the haltc register is set high. the system leaves the power down mode by means of an external reset, an interrupt, an external transition signal on port a, or a wdt overfow. an external reset causes a device initialisation, and the wdt overfow performs a warm reset. after examining the to and pdf fags, the reason for the device reset can be determined. the pdf fag is cleared by system power-up or by executing the clr wdt instruction, and is set by executing the halt instruction. on the other hand, the to fag is set if wdt time-out occurs, and causes a wake-up that only resets the program counter and sp, and leaves the others in their original state.
rev. 1.20 ?4 ?a? ?0? 201? rev. 1.20 ?5 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale the port a wake-up and interrupt methods can be considered as a continuation of normal execution. each pin of port a can be independently selected to wake-up the device using configuration options. after awakening from an i/o port stimulus, the program will resume execution at the next instruction. however, if awakening from an interrupt, two sequences may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. but if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. when an interrupt request flag is set before entering the halt status, the system cannot be awakened using that interrupt. if a wake-up events occur, it takes a number of clock cycles to resume normal operation. in other words, a dummy period is inserted after the wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is fnished. to minimise power consumption, all the i/o pins should be carefully managed before entering the halt status. the accompanying table illustrates the wake-up delay time for different system clock sources.the sst time is decided by sst confguration option and the oscon bit in the haltc register. fsys clock source sst selection oscon sst time ( n: number of fsys clock ) xtal 0 0 n= 1024 0 1 n= 2 1 0 n= 1024 1 1 n= 2 erc 0 0 n= 1024 0 1 n= 2 1 0 n= 2 1 1 n= 2 hirc 0 0 n= 1024 0 1 n= 2 1 0 n= 2 1 1 n= 2 required wake-up clock cycles haltc register bit 7 6 5 4 3 2 1 0 name oscon lcdon r/w r/w r/w por 0 0 bit 7 o s con : system oscillator state in the power down mode 0: system oscillator stops running 1: system oscillator keeps running bit 6~1 unimplemented, read as 0 bit 0 lcdon : lcd module state in the power down mode 0: lcd state is determined by the lcd_on confguration option 1: lcd module remains on (if the f sub is active) regardless of the confguration option setting
rev. 1.20 ?6 ?a? ?0? 201? rev. 1.20 ?7 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defned state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power- on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=100ms power-on reset timing chart for the application a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for the application that operate s within an environment where more noise is present the enhanced reset circuit shown is recommended.
rev. 1.20 ?6 ?a? ?0? 201? rev. 1.20 ?7 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale note: * it is recommended that this component is added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. external res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time= 100ms res reset timing chart low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device . the lvr function has a specifc lvr voltage v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the wdtc1 register will also be set to 1 . the lvr includes the following specifcations: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ignore it and will not perform a reset function. one of a range of specifed voltage values for v lvr can be selected by the lvs bits in the lvrc register. if the lvs7~lvs0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the lvr will reset the device after 2~3 lirc clock cycles. w hen this happens, the lrf bit in the wdtc1 register will be set to 1. after power on the register will have the value of 0 1010 101b. note that the lvr function will be automatically disabled when the device enters the power down mode. note: t rstd is power-on delay, typical time= 100ms low voltage reset timing chart
rev. 1.20 ?8 ?a? ?0? 201? rev. 1.20 ?9 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs2 lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 lvs7 ~ lvs0 : lvr voltage select 01010101: 2.1v (default) 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v other values: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned register values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value. watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out fag to will be set to 1 . note: t rstd is power-on delay, typical time= 100ms wdt time-out reset during normal operation timing chart watchdog time-out reset during power down mode the watchdog time-out reset during power down mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to fag will be set to 1 . refer to the a.c. characteristics for t sst details. note: the t sst can be chosen to be either 1024 or 2 clock cycles via confguration option if the system clock source is provided by erc or hirc. the sst is 1024 for hxt or lxt. wdt time-out reset during power down timing chart reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset fags are shown in the table .
rev. 1.20 ?8 ?a? ?0? 201? rev. 1.20 ?9 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale to pdf reset conditions 0 0 p ower-on reset u u res or lvr reset during n ormal operation 0 1 res wake-up halt 1 u wdt time-out reset during normal operation 1 1 wdt wake-up halt note: u stands for unchanged. the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset? wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* iar0 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ?p0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu iar1 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ?p1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp ---0 --00 ---0 --00 ---0 --00 ---0 --00 ---u --uu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ctrl0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu lvrc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu t?r0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu t?r0c 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu t?r1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu t?r1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu t?r1c 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu pbc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu
rev. 1.20 40 ?a? ?0? 201? rev. 1.20 41 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* daco --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu ftrc 0--0 --00 0--0 --00 0--0 --00 0--0 --00 u--u --uu adcr -000 x000 -000 x000 -000 x000 -000 x000 -uuu uuuu swc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu adcd 0000 -111 0000 -111 0000 -111 0000 -111 uuuu -uuu wdtc1 0101 0x11 0101 0x11 0101 0x11 0101 0x11 uuuu uuuu wdtc 111- ss01 111- ss01 111- ss01 111- ss01 uuu- uuuu wdtd 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu Cuuu chprc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu t?r2h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu t?r2l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu t?r2c 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu sgc 0--0 ---- 0--0 ---- 0--0 ---- 0--0 ---- u--u ---- sgdnr ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu sgn --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu haltc 0--- ---0 0--- ---0 0--- ---0 0--- ---0 u--- ---u lcdout 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu ctrl1 00-- --01 00-- --01 00-- --01 00-- --01 uu-- --uu vibrc ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u iadac 0-00 0000 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pawk 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu papu -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu pbpu --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu pcpu 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu sfs ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu opac 0--- 0000 0--- 0000 0--- 0000 0--- 0000 u--- uuuu lcdc 00-0 -000 00-0 -000 00-0 -000 00-0 -000 u u-u -uuu ?fic -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu iac0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu iac1 1111 00-1 1111 00-1 1111 00-1 1111 00-1 uuuu uu-u tk?0c4 -000 ---0 -000 ---0 -000 ---0 -000 ---0 -uuu ---u tk?016dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tk?016dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tk?010dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tk?0ro 0000 0001 0000 0001 0000 0001 0000 0001 uuuu uuuu tk?0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tk?0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tk?0c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tk?0c? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu note : *stands for warm reset "-" not implement "u" stands for "unchanged" "x" stands for "unknown" "s" for special case, it depends on the option table (please see the wdt chapter for the detail)
rev. 1.20 40 ?a? ?0? 201? rev. 1.20 41 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. most pins can have either an input or output designation under user program control. additionally, as there are pull-high resistors and wake-up software confgurations, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list register name por bit 7 6 5 4 3 2 1 0 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk ? pawk2 pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac ? pac2 pac1 pac0 papu 00h papu6 papu5 papu4 papu ? papu2 papu1 papu0 pbc ? fh pbc5 pbc4 pbc? pbc2 pbc1 pbc0 pbpu 00h pbpu5 pbpu4 pbpu? pbpu2 pbpu1 pbpu0 pcc ffh pcc7 pcc6 pcc5 pcc4 pcc? pcc2 pcc1 pcc0 pcpu ffh pcpu7 pcpu6 pcpu5 pcpu4 pcpu? pcpu2 pcpu1 pcpu0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via a register known as papu, pbpu and pcpu located in the data memory. the pull-high resistors are implemented using weak pmos transistors. note that pin pa7 does not have a pull-high resistor selection. papu register bit 7 6 5 4 3 2 1 0 name papu6 papu5 papu4 papu ? papu2 papu1 papu0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 ~0 papu : i/o port bit 6 ~ bit 0 pull-high control 0: disable 1: enable pbpu register bit 7 6 5 4 3 2 1 0 name pbpu5 pbpu4 pbpu? pbpu2 pbpu1 pbpu0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 ~0 pbpu : i/o port bit 5 ~ bit 0 pull-high control 0: disable 1: enable
rev. 1.20 42 ?a? ?0? 201? rev. 1.20 4? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale pcpu register bit 7 6 5 4 3 2 1 0 name pcpu7 pcpu6 pcpu5 pcpu4 pcpu? pcpu2 pcpu1 pcpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 pcpu : i/o port bit 7 ~ bit 0 pull-high control 0: disable 1: enable port a wake-up if the halt instruction is executed, the device will enter power down mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the pa0~pa7 pins from high to low. after a halt instruction forces the microcontroller into entering power down mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applications that can be woken up via external switches. note that pins pa0 to pa7 can be selected individually to have this wake-up feature using an internal register known as pawk, located in the data memory. pawu register bit 7 6 5 4 3 2 1 0 name pawk7 pawk6 pawk5 pawk4 pawk ? pawk2 pawk1 pawk0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 paw u : port a bit 7 ~ bit 0 wake-up control 0: disable 1: enable i/o port control registers each port has its own control register, known as pac, pbc and pcc which controls the input/ output configuration. with this control register, each i/o pin with or without pull-high resistors can be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name pac7 pac6 pac5 pac4 pac ? pac2 pac1 pac0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 pac : i/o port bit 7 ~ bit 0 input/output control 0: output 1: input
rev. 1.20 42 ?a? ?0? 201? rev. 1.20 4? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale pbc register bit 7 6 5 4 3 2 1 0 name pbc5 pbc4 pbc? pbc2 pbc1 pbc0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5 ~0 pbc : i/o port bit 5 ~ bit 0 input/output control 0: output 1: input pcc register bit 7 6 5 4 3 2 1 0 name pcc7 pcc6 pcc5 pcc4 pcc? pcc2 pcc1 pcc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 pcc : i/o port bit 7 ~ bit 0 input/output control 0: output 1: input pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by confguration options while for others the function is set by application program control. external interrupt input the external interrupt pin, int, is pin-shared with an i/o pin. to use the pin as an external interrupt input the correct bits in the intc0 register must be programmed. the pin must also be setup as an input by setting the pbc4 bit in the port control register. a pull-high resistor can also be selected via the appropriate port pull-high resistor register. note that even if the pin is setup as an external interrupt input the i/o function still remains. external timer/event counter input the timer/event counter pins, tmr 0, tmr 1 and tmr 2 are pin-shared with i/o pins. for these shared pins to be used as timer/event counter inputs, the timer/event counter must be confgured to be in the event counter or pulse width measurement mode. this is achieved by setting the appropriate bits in the timer/event counter control register. the pins must also be setup as inputs by setting the appropriate bit in the port control register. pull-high resistor options can also be selected using the port pull-high resistor registers. note that even if the pin is setup as an external timer input the i/o function still remains. buzzer output the buzzer function output is pin-shared with an i/o pin. the output function of this pin is chosen using the sfs register. note that the corresponding bit of the port control register, must setup the pin as an output to enable buzzer output. if the port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if buzzer function has been selected.
rev. 1.20 44 ?a? ?0? 201? rev. 1.20 45 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale lcd driver pins pins p c 0~p c7 on port c can be used as lcd seg driver pins. this function is controlled using the lcdout register. touch key pins pins pb0~pb3 are pin-shared with touch key function. this function is controlled using the tkm0c2 register . i/o pin structures the diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins.
??? ? ? ?-
? ? ?? ?? ? ?- ?
? - ? ?? ?? ? ?-
?
? ?? ? ?? ? ?-
? ? - ?-
? ? - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ? ?? ? ? ?? ? generic input/output ports

? ? ? ? ?
pa7 nmos input/output port
rev. 1.20 44 ?a? ?0? 201? rev. 1.20 45 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, the i/ o data register and i/o port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register is frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
read modify write timing pins pa0 to pa7 each have a wake-up function, selected via the pawk register. when the device is in the idle/sleep mode, various methods are available to wake the device up. one of these is a high to low transition of any of these pins. single or multiple pins on port a can be setup to have this function. timer/event counter s three timer/event counters are implemented in the microcontroller. timer/event counter 0 contains an 8-bit programmable count-up counter whose clock may come from an external source or an internal clock source. an internal clock source comes from f sys or the internal low frequency clock known as fl. timer/event counter 1 contains a 16-bit programmable count-up counter whose clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4 or the internal low frequency clock known as fl. the clock fl is derived from the lirc or lxt oscillator and can be selected by the low frequency selection bit lfs bit in the ctrl0 register. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. timer/event counter 2 contains a 16-bit programmable count-up counter whose clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4 or the timer/event counter 2 internal clock f tck . the clock f tck may come from the low frequency clock f l or the clocks generated from the touch key module named f ref , fsen and f tmck described in the touch key function section. the clock is selected using the timer/event counter 2 clock source selection bits tcks1 and tck0 in the ctrl0 register. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are two registers related to the timer/event counter 0; tmr0 and tmr0c.writing to tmr0 puts the starting value in the timer/event counter 0 register and reading tmr0 reads out the contents of timer/event counter 0. the tmr0c is a timer/event counter control register, which defines the overall operations. there are three registers related to the timer/event counter 1; tmr1h, tmr1l and tmr1c. writing to tmr1l will only put the written data into an internal lower-order byte buffer (8-bit) while writing to tmr1h will transfer the specified data and the contents of the lower-order byte buffer to both the tmr1h and tmr1l registers, respectively.
rev. 1.20 46 ?a? ?0? 201? rev. 1.20 47 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale the timer/event counter 1 preload register is changed when each time there is a write operation to tmr1h. reading tmr1h will latch the contents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading tmr1l will read the contents of the lower-order byte buffer. tmr1c is the timer/event counter 1 control register, which defnes the operating mode, counting enable or disable, the tmr1 active edge and the prescaler stage selections. also there are three registers related to the timer/event counter 2 named tmr2h, tmr2l and tmr2c. the operations of reading from and writing to the timer/event counter 2 registers named tmr2h and tmr2l are the same with timer/event counter 1 described above. the txm0 and txm1 bits in tmrxc register where x may be equal to 0, 1 or 2 defne the operation mode. the event count mode is used to count external events, which means that the clock source must come from the external (tmr0, tmr1 or tmr2) pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count a high or low level duration of an external signal on the tmr0, tmr1 or tmr2 pins with the timing based on the internally selected clock source. in the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at ffh for -8-bit counter or ffffh for 16- bit counter. once an overfow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request fag, t0f, t1f or t2f. in the pulse width measurement mode with the values of the timer enable control bit txon and the active edge control bit txe equal to 1, after the tmrx pin has received a transient from low to high (or high to low if the txe bit is 0), it will start counting until the tmrx pin returns to the original level and resets the txon bit. the measured result remains in the timer/event counter even if the activated transient occurs again. therefore, only a 1-cycle measurement can be made until the txon bit is again set. the cycle measurement will re-function as long as it receives further transient pulses. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overfows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes.

?
? ? ? ? ? ? - ? ? ?? ? ? ? ? ? ? ??? ? ? ? ?? ? ? ? ?? ?? ? ?? ? ??? ??? ?? ? ? timer/event count 0
? ? ? ? ? ? ? ? ? ? -
? ? ? ? ? ? ? ?? ?? ? ? ?? ? ? ? ??? ?? ? ? ? ? ?
?? ?? ? ? ? ? ??? ??? ? ? ? ? timer/event count 1
rev. 1.20 46 ?a? ?0? 201? rev. 1.20 47 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale

? ? ? ? ? ? ? ? - ? ? - ?? ? ? ?? ?? ? ?? ?? ? ? ? ? ??? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ??? ?-? ? ? ? ? ? ? ?? ? ?? ? ? ? ??? ? ?? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? timer/event count 2 tmr0c register bit 7 6 5 4 3 2 1 0 name t 0 ?1 t 0 ?0 t 0 s t 0 on t 0 e t0psc2 t0psc1 t0psc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 0 0 0 bit 7~6 t0m1, t0m0 : timer0 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width measurement mode bit 5 t0s : timer clock source 0: f sys 1: low frequency clock f l bit 4 t0on : timer/event counter counting enable 0: disable 1: enable bit 3 t 0 e : event counter active edge selection 0: count on rising edge 1: count on falling edge pulse width measurement active edge selection 0: start counting on falling edge, stop on rising edge 1: start counting on rising edge, stop on falling edge bit 2~0 t0psc2, t0psc1, t0psc0 : timer prescaler rate selection timer internal clock (f int0 )= 000: f t0 001: f t0 /2 010: f t 0 /4 011: f t 0 /8 100: f t 0 /16 101: f t 0 /32 110: f t 0 /64 111: f t 0 /128
rev. 1.20 48 ?a? ?0? 201? rev. 1.20 49 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale tmr 1 c register bit 7 6 5 4 3 2 1 0 name t1?1 t1?0 t1s t1on t1e t 1 psc2 t 1 psc1 t 1 psc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 0 0 0 bit 7~6 t1m1, t1m0 : timer0 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width measurement mode bit 5 t1s : timer clock source 0: f sys /4 1: low frequency clock f l bit 4 t1on : timer/event counter counting enable 0: disable 1: enable bit 3 t 1 e : event counter active edge selection 0: count on rising edge 1: count on falling edge pulse width measurement active edge selection 0: start counting on falling edge, stop on rising edge 1: start counting on rising edge, stop on falling edge bit 2~0 t1psc2, t1psc1, t1psc0 : timer prescaler rate selection timer internal clock (f int1 )= 000: f t1 001: f t1 /2 010: f t 1 /4 011: f t 1 /8 100: f t 1 /16 101: f t 1 /32 110: f t 1 /64 111: f t 1 /128
rev. 1.20 48 ?a? ?0? 201? rev. 1.20 49 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale tmr2c register bit 7 6 5 4 3 2 1 0 name t2?1 t2?0 t2s t2on t2e t2psc2 t2psc1 t2psc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 0 0 0 bit 7~6 t2m1, t2m0 : timer0 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width measurement mode bit 5 t2s : timer clock source 0: f sys /4 1: f tck bit 4 t2on : timer/event counter counting enable 0: disable 1: enable bit 3 t 2 e : event counter active edge selection 0: count on rising edge 1: count on falling edge pulse width measurement active edge selection 0: start counting on falling edge, stop on rising edge 1: start counting on rising edge, stop on falling edge bit 2~0 t2psc2, t2psc1, t2psc0 : timer prescaler rate selection timer internal clock (f int2 )= 000: f t2 001: f t2 /2 010: f t 2 /4 011: f t 2 /8 100: f t 2 /16 101: f t 2 /32 110: f t 2 /64 111: f t 2 /128
rev. 1.20 50 ?a? ?0? 201? rev. 1.20 51 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale timer mode in this mode, the timer/event counter can be utilised to measure fxed time intervals, providing an internal interrupt signal each time the timer/event counter overfows. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 1 0 in this mode the internal clock is used as the timer clock. the timer input clock source is either f sys , f sys /4, f l or f tck . however, this timer clock source is further divided by a prescaler, the value of which is determined by the bits tnpsc2~tnpsc0 in the timer control register. the timer-on bit, tnon must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. a timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the etni bits of the intc0 and mfic register are reset to zero.
timer mode timing chart event counter mode in this mode, a number of externally changing logic events, occurring on the external timer tmrn pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 0 1 in this mode, the external timer tmrn pin is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, tne, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the tne is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is confgured to operate as an event counter input pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting
rev. 1.20 50 ?a? ?0? 201? rev. 1.20 51 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale mode, the second is to ensure that the port control register confgures the pin as an input. it should be noted that in the event counting mode, even if the is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input tmrn pin. as a result when the timer overfows it will generate a timer interrupt and corresponding wake-up source. event counter mode timing chart (t n e=1) pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. to operate in this mode, the operating mode select bit pair, tnm1/ tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width capture mode bit7 bit6 1 1 i n this mode the internal clock, f sys , f sys /4, f l or f tck , is used as the internal clock for the 8-bit timer/event counter and the 16-bit timer/event counter. however, the clock source, f sys and f sys /4, for the 8-bit timer and the 16-bit timer are further divided by a prescaler, the value of which is determined by the prescaler rate select bits tnpsc2~tnpsc0, which are bits 2~0 in the timer control register. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit tne, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width measurement mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the tmrn pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. the timer cannot begin further pulse width measurement until the enable bit is set high again by the program. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero.
rev. 1.20 52 ?a? ?0? 201? rev. 1.20 5? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale as the tmrn pin is shared with an i/o pin, to ensure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width measurement mode, the second is to ensure that the port control register confgures the pin as an input.
?? ? ? ? ? ? pulse width measurement mode timing chart (t n e=0) prescaler bits tnpsc0~tnpsc2 of the tmrnc register can be used to defne a division ratio for the internal clock source of the timer/event counter enabling longer time out periods to be setup. buzzer operating in a similar way to the programmable frequency divider, the buzzer function provides a means of producing a variable frequency output, suitable for applications such as piezo-buzzer driving or other external circuits that require a precise frequency generator. the bz and bz pins form a complimentary pair, and are pin-shared with i/o pins, pa 1 and pa 2 . note that the bz pin is the inverse of the bz pin which together generate s a differential output which can supply more power to connected interfaces such as buzzers. the pa1 and pa2 are setup as i/o pins or buzzer pins using the sfs register . the buzzer is driven by the timer/event counter 0 or timer/event counter 1 overflow signal divided by 2 selected by the clock source selection bit named bzcs in ctrl1 register. if the software options have selected both pins pa1 and pa2 to function as a bz and bz complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits pac1 and pac2 of the pac port control register to zero. the pa1 data bit in the pa data register must also be set high to enable the buzzer outputs, if set low, both pins pa1 and pa2 will remain low. in this way the single bit pa1 of the pa data register can be used as an on/off control for both the bz and bz buzzer pin outputs. note that the pa2 data bit in the pa data register has no control over the bz buzzer pin pa2. if software options have selected that only the pa1 pin is to function as a bz buzzer pin, then the pa2 pin can be used as a normal i/o pin. for the pa1 pin to function as a bz buzzer pin, pa1 must be setup as an output by setting bit pac1 of the pac port control register to zero. the pa1 data bit in the pa data register must also be set high to enable the buzzer output, if set low pin pa1 will remain low. in this way the pa1 bit can be used as an on/off control for the bz buzzer pin pa1. if the pac1 bit of the pac port control register is set high, then pin pa1 can still be used as an input even though the software option has confgured it as a bz buzzer output.
rev. 1.20 52 ?a? ?0? 201? rev. 1.20 5? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale bzbs bzs pac 2 pa c1 pa 2 pa 1 function 1 1 0 0 x 1 pa1= bz ? pa2= bz 1 1 0 0 x 0 pa1= "0" ? pa2= "0" 1 1 0 1 x 1 pa1= "input" ? pa2= bz 1 1 0 1 x 0 pa1= "input" ? pa2= "0" 1 1 1 0 x 1 pa1= bz ? pa2= "input" 1 1 1 0 x 0 pa1= "0" ? pa2= "input" x x 1 1 x x pa1= "input" ? pa2= "input" 0 0 x x x x pa1= "i/o" ? pa2= "i/o" "" stands for don t care s fs register bit 7 6 5 4 3 2 1 0 name bzbs bzs r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1 bzb s : pa2 function selection 0: i/o 1: bz bit 0 bzs : pa1 function selection 0: i/o 1: bz when register sfs select s the i/o function, the related control refers to the port a control register.
buzzer output pin control
rev. 1.20 54 ?a? ?0? 201? rev. 1.20 55 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale i/o interfacing the timer/event counter, when confgured to run in the event counter or pulse width measurement mode, requires the use of an external timer pin for its operation. as this pin is a shared pin it must be confgured correctly to ensure that it is setup for use as a timer/event counter input pin. this is achieved by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. additionally the corresponding port control register bit must be set high to ensure that the pin is setup as an input. any pull-high resistor connected to this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly initialised before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is frst loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. when the timer/event counter overfows, its corresponding interrupt request fag in the interrupt control register will be set. if the timer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a timer/event counter overfow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overfow occurs the device will be woken up from its power- down condition. to prevent such a wake-up from occurring, the timer interrupt request fag should frst be set high before issuing the halt instruction to enter the idle/sleep mode.
rev. 1.20 54 ?a? ?0? 201? rev. 1.20 55 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale timer program example the program shows how the timer/event counter registers are setup along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counters to be in the timer mode, which uses the internal system clock as their clock source. pfd programming example o rg 04h ;external interrupt vector org 0 c h ;timer counter 0 interrupt vector jmp tmr0int ;jump here when timer 0 overfows : : o rg 20h ;main program : : ;internal timer 0 interrupt routine tmr0int: : : ;timer 0 main program placed here : : begin: ;setup timer 0 registers m ov a,09bh ;setup timer 0 preload value mov tmr0,a mov a,081h ;setup timer 0 control register mov tmr0c,a ;timer mode and prescaler set to /2 ;setup interrupt register m ov a,00 5 h ; enable master interrupt and both timer interrupts mov intc0,a : : s et tmr0c.4 ;start timer 0 : :
rev. 1.20 56 ?a? ?0? 201? rev. 1.20 57 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale vibration sensor amplifer the device contains a vibration sensor amplifer to amplify small signal input s , generated from vibration sensors. when the sensor is connected to the vibration input pin, namely vib, and a small signal resulting from vibration detection is generated on the vib pin, the internal amplifier will amplify the signal to generate a wake-up source to wake up the device from the power down mode. the vibration sensor amplifer can be enabled or disable by the control bit, vibren, in the vibrc register to save power.

vibrc register bit 7 6 5 4 3 2 1 0 name vibren r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 vibren : vibration sensor amplifer control 0: disabled 1: enabled touch key module the device contains four touch key s . the touch key function s are fully integrated and require no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. touch key structure the touch keys are pin shared with the pb logic i/o pins, with the desired function chosen via register bits. touch key register defnition the touch key functions have their own suite of registers. the following table shows the register set together with a basic description. name usage tk? 0 16dh 16-bit c/f counter high b?te tk? 0 16dl 16-bit c/f counter low b?te tk?010dl 10-bit counter low b?te tk?0ro internal capacitor select tk? 0 c0 control register 0 key select/x2 freq/flter control/frequency select tk? 0 c1 control register 1 sensor oscillator control/ touch ke? or i/o select . tk? 0 c2 control register 2 counter on-off and clear control/reference clock control/ s tart bit tk? 0 c? control register 3 counter overfow bits /reference oscillator overfow time select tk?0c4 control register 4 f vdd clock source select/power control register listing
rev. 1.20 56 ?a? ?0? 201? rev. 1.20 57 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale register name bits 7 6 5 4 3 2 1 0 tk? 0 16dh d7 d6 d5 d4 d? d2 d1 d0 tk? n16dl d7 d6 d5 d4 d? d2 d1 d0 tk?010dl d7 d6 d5 d4 d? d2 d1 d0 tk?0ro d7 d6 d5 d4 d? d2 d1 d0 tk? 0 c0 ?0?xs1 ?0?xs0 ?0dfen ?0filen ?0sofc ?0sof2 ?0sof1 ?0sof0 tk? 0 c1 ?0k4oen ?0k?oen ?0k2oen ?0k1oen ?0k4io ?0k?io ?0k2io ?0k1io tk? 0 c2 ? 016cton ? 010cton ?0st ?0roen ?0rcclr ?016ctclr ?010ctclr ?0ros tk? 0 c? d9 d8 ?0rcov ? 016ctov ? 010ctov ?0rovs2 ?0rovs1 ?0rovs0 tk?0c4 fvdd2 fvdd1 fvdd0 nor? register content summary tkm016dh register bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d12 d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d15~d8 : touch key module 16-bit counter (tmcnt) high byte. tkm016dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : touch key module 16-bit counter (tmcnt) low byte. tkm010dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : t ouch key module 1 0 -bit counter (tmcnt) bit 7~ bit 0. tkm0ro register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 1 bit 7~0 d7~d0 : integrated osc capacitor can select tkmorcc[7:0]50pf/256. it is not permitted to write a 00h value to this register.
rev. 1.20 58 ?a? ?0? 201? rev. 1.20 59 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale tkm0c0 register bit 7 6 5 4 3 2 1 0 name ?0?xs1 ?0?xs0 ?0dfen ?0filen ?0sofc ?0sof2 ?0sof1 ?0sof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 m0mxs1 ~ m0mxs 0 : multiplexer key select. 00: key 1 01: key 2 10: key 3 11: key 4 bit 5 m0dfen : double frequency function control 0: disable 1: enable bit 4 m0filen : flter function control 0: disable 1: enable bit 3 m0sofc : c to f osc frequency hopping function select 0: frequency hopping is controlled by software and c to f osc micro adjustment frequency is determined by the m0sof2~m0sof0 bits 1: frequency hopping controlled by hardware - m0sof2~m0sof0 bits have no effect. here the counters three msbs, selected by m0rovs2~m0rovs0, will automatically adjust the c to f osc micro adjustment frequency. bit 2~0 m0sof2 ~ m0sof 0 : c to f osc frequency hopping frequency select 000: 400 khz 001: 425 khz 010: 450 khz 011: 475 khz 100: 500 khz 101: 525 khz 110: 550 khz 111: 575 khz
rev. 1.20 58 ?a? ?0? 201? rev. 1.20 59 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale tkm0c1 register bit 7 6 5 4 3 2 1 0 name ?0k4oen ?0k?oen ?0k2oen ?0k1oen ?0k4io ?0k?io ?0k2io ?0k1io r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 m0k4oen : key 4 sensor oscillat or control 0: disable 1: enable bit 6 m0k 3 oen : key 3 sensor oscillat or control 0: disable 1: enable bit 5 m0k 2 oen : key 2 sensor oscillat or control 0: disable 1: enable bit 4 m0k 1 oen : key 1 sensor oscillat or control 0: disable 1: enable bit 3 m0k4io : key 4 touch key input or i/o function 0: i/o 1: touch key inpu t bit 2 m0k 3 io : key 3 touch key input or i/o function 0: i/o 1: touch key input bit 1 m0k 2 io : key 2 touch key input or i/o function 0: i/o 1: touch key input bit 0 m0k 1 io : key 1 touch key input or i/o function 0: i/o 1: touch key input
rev. 1.20 60 ?a? ?0? 201? rev. 1.20 61 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale tkm0c2 register bit 7 6 5 4 3 2 1 0 name ? 016cton ? 010cton ?0st ?0roen ?0rcclr ?016ctclr ?010ctclr ?0ros r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 m016cton : 16-bit c/f counter control 0: disable 1: enable this bit is clear ed by hardware when the m0rcov bit is set to 1. bit 6 m010cton : 1 0 -bit counter control 0: disable 1: enable this bit is clear ed by hardware when the m0rcov bit is set to 1 . bit 5 m0 st : start f tmck and f vddck output clock 0: h ardware set s enck to low , r eference o scillator 13-stage counter stop s 01: e nable the f tmck and f vddck output clock - hardware set s enck to high . h ardware set s clears the m0rcov flag low and the reference oscillator 13-stage counter start count ing . if the counter overfow s , the m0rcov fag is set to 1, the hardware clears enck to low and the touch key interrupt request fag , tkf, will be set. a touch key interrupt will be generated if the touch key interrupt enable bit, tke , and the global interrupt bit, emi , are set to 1 . bit 4 m0roen : reference clock control 0: disable 1: enable bit 3 m0rcclr : c lear reference oscillator 13-stage counter 0: no change 1: clear counter the hardware circuit will clear this bit to zero after it is set to 1 by the user. bit 2 m016ctclr : 16-bit c/f c ounter clear control 0: no change 1: clear counter ha rdware will clear this bit to zero after it is set to 1 by user. bit 1 m01 0 ctclr : 1 0 -bit counter clear control 0: no change 1: clear counter h ardware will clear this bit to zero after it is set to 1 by user. bit 0 m0ros : reference oscillator 13-stage c ounter clock source select 0: reference osc 1: key 4 sensor osc
rev. 1.20 60 ?a? ?0? 201? rev. 1.20 61 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale tkm0c3 register bit 7 6 5 4 3 2 1 0 name d9 d8 ?0rcov ? 016ctov ? 010ctov ?0rovs2 ?0rovs1 ?0rovs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 d9 ~ d 8 : fvdd 10-bit c ounter b it 9 and b it 8 bit 5 m0rcov : 13-stage c ounter o verfow f lag 0: no overfow 1: overfow if the 13-stage counter overfow s , the touch key interrupt request fag , tkf, will be set and the hardware will clear enck to low to disable the ftmck and fvddck output s . bit 4 m016ctov : 16-bit c/f c ounter o verfow f lag 0: no overfow 1: overfow this bit must be clear ed by software. bit 3 m01 0 ctov : 1 0 -bit c ounter o verfow f lag 0: no overfow 1: overfow this bit must be clear ed by software. bit 2~0 m0rovs2 ~ m0rovs 0 : reference oscillator 13-stage c ounter o verfow t ime select s witch 0 control bits: 000: 64 counts 001: 128 counts 010: 256 counts 011: 512 counts 100: 1024 counts 101: 2048 counts 110: 4096 counts 111: 8192 counts tkm0c4 register bit 7 6 5 4 3 2 1 0 name fvdd2 fvdd1 fvdd0 nor? r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~4 fvdd2 ~ fvdd 0 : fvdd c lock s ource s elect 000: f sys /2 001: f sys / 4 010: f sys / 8 011: f sys / 16 100: f sys / 32 101: f sys / 64 110: f sys / 128 111: f s ub bit 3~1 unimplemented, read as 0 bit 0 norm : normal/ low power mode select 0: low power mode 1: n ormal mode
rev. 1.20 62 ?a? ?0? 201? rev. 1.20 6? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale touch key operation when a fnger touches or is in proximity to a touch pad, the capacitance of the pad will increase. by using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. using an internal programmable divider the reference clock is used to generate a fixed time perio d . by counting a number of generated clock cycles from the sense oscillator during this fxed time period touch key actions can be determined. the device contains four touch key inputs which are shared with logical i/o pin s , with the desired function selected using register bits. the touch key module also has its own interrupt vector s and set of interrupts fags. during this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. at the end of the fxed reference clock time interval, a touch key interrupt signal will be generated.

?
?

?
?
touch switch module block diagram

touch key or i/o function select
rev. 1.20 62 ?a? ?0? 201? rev. 1.20 6? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale touch key interrupt s the touch key module, which consists of four touch keys, has three independent interrupts, an overall touch key interrupt as well as one for the 16-bit c/f counter and one for the 10- bit counter. the 16-bit c/f counter and 10-bit counter interrupts are contained within the multi-function interrupts and therefore do not have their own vector s . care must be taken during programming as the se counter interrupt fags contained within the multi-function interrupts will not be automatically reset upon entry into the interrupt service routine but rather must be reset manually by the application program. more details regarding the touch key interrupts are located in the interrupt section of the datasheet. programming considerations after the relevant registers are setup, the touch key detection process is initiated the changing the m0st bit from low to high. this will enable and synchronise all relevant oscillators. charge pump and voltage regulator one charge pump and one voltage regulator are implemented in this device as way of providing a stable voltage source for certain internal functions. an additional bandgap voltage source is also provided . operation the charge pump can be enabled or disabled by the application program. the charge pump uses vdd as its input, and has the function of doubling the vdd voltage. the output voltage of the charge pump will be vdd 2. the regulator can generate a stable voltage of 3.3v, which is used by the internal wdt and a/d converter and can also provide an external bridge sensor excitation voltage or supply a reference voltage for other applications. the user needs to guarantee that the charge pump output voltage is greater than 3.6v to ensure that the regulator generates the required 3.3v voltage output. the block diagram of this module is shown below. charge pump ( voltage doubler ) vdd op adc vochp voreg chpc 1 chpc 2 vdd vdd ? 2 divider fs chpckd regen chpen regulator ( ? . ? v ) ? . ? v charge pump and r e gulator block diagram
rev. 1.20 64 ?a? ?0? 201? rev. 1.20 65 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale additionally, the device also includes a band gap voltage generator for the 1.5v low temperature sensitive reference voltage. this reference voltage is used as the zero adjustment and for a single end type reference voltage.

? ?? ? ? ? ?? ? rfil is about 100 k and the recommend cfil is 10 f. note: the vobgp signal is only for internal used. it must not be connected to external components except for the recommend cfil capacitor. there is a single register associated with this module named chprc. the chprc is the charge pump/regulator control register, which controls the charge pump on/off, regulator on/off functions as well as a clock divider value to generate the charge pump cloc k. the chpckd4~chpckd0 bits are use to set the clock divider to generate the desired clock frequency for proper charge pump operation. the actual frequency is determined by the following formula. actual charge pump clock= (f sys /16) / (chpckd +1). chprc register bit 7 6 5 4 3 2 1 0 name chpckd4 chpckd? chpckd2 chpckd1 chpckd0 bgpqst chpen regen r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~3 chpckd4 ~ chpckd 0 : the charge pump clock divider these 5 bits select the c lock divide r ration of 1~32. charge pump clock = (f sys /16) / (chpckd+1) bit 2 bgpqst : bandgap quick start-up function 0: r short, quickly start 1: r connected, normal rc flter mode every time when regen change s from 0 to 1 ( r egulator turn s on) , t his bit should be set to 0 and then set to 1 to make sure the bandgap stabilise s quickly ( t he minimum time is about 2ms now). bit 1 chpen : charge pump on/off control 0: disable 1: enable note: this bit will be ignore d if the regen is disabled. bit 0 regen : regulator/charge-pump module on/off control 0: disable 1: enable
rev. 1.20 64 ?a? ?0? 201? rev. 1.20 65 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale regen chpen charge pump vochp pin regulator voreg pin opa, adc body fat circuit description 0 off vdd off hi- impedance disable w hole module is disable d ? opa/ adc/bod? fat circuit will lose power 1 0 off vdd on ?.?v active use d when v dd is greater than ?.6v (v dd > ?.6v) 1 1 on 2vdd on ?.?v active use when v dd is less than ?.6v (v dd = 2.2v - ?.6v) the suggested charge pump clock frequency is 20 k hz. the application needs to set the correct value to get the desired clock frequency. for a 4mhz application, the chpckd bits should be set to the value 11, and for a 2mhz application, the bits should be set to 5. the regen bit in the chprc register is the regulator/charge-pump module enable/disable control bit. if this bit is disabled, then the regulator will be disabled and the charge pump will be also be disabled to save power. when regen= 0, the module will enter the p ower d own m ode ignoring the chpen setting. the a/d converter and opa will also be disabled to reduce power. if regen is set to 1, the regulator will be enabled. if chpen is enabled, the charge pump will be active and will use v dd as its input to generate the double voltage output. this double voltage will be used as the input voltage for the regulator. if chpen is set to 0, the charge pump is disabled and the charge pump output will be equal to the charge pump input v dd . it is necessary to take care of the v dd voltage. if the voltage is less than 3.6v, then chpen should be set to 1 to enable the charge pump, otherwise chpen should be set to zero. if the charge pump is disabled and v dd is less than 3.6v then the output voltage of the regulator will not be guaranteed. dual slope a/d converter a dual slope a/d convert e r is implemented in the device . the dual slope module includes an instrumentation amplifier, a programmable gain amplifier, for the amplification of differential signals, an integrator and a comparator for the main dual slope ad convertor. there are two special function registers related to this function known as adcr and adcd. the adcr register is the a/d control register, which controls the adc block power on/off, the chopper clock on/off, the charge/discharge control and is also used to read out the comparator output status. the adcd register is the a/d chopper clock divider register, which defnes the chopper clock to the adc module. the adpwren bit, defned in adcr register, is used to control the adc module on/off function. the adccken bit, defined in the adcr register, is used to control the chopper clock on/off function. when adccken is set to 1 it will enable the chopper clock, with the clock frequency defned by the adcd register. the adc module includes the opa, pga, integrator and comparator. however, the bandgap voltage generator is independent of this module. it will be automatically enabled when the regulator is enabled, and also be disabled when the regulator is disabled. the application program should enable the related power to permit them to function and disable them when entering the power down mode to conserve power. the charge/discharge control bits, addisch1 and addisch0, are used to control the dual slope circuit charging and discharging behavior. the adcmpo bit is read only for the comparator output, while the adintm bits can set the adcmpo trigger mode for interrupt generation. the adc pga input signal can come from the dchop or th/lb pin selected by the adis selection bit in adcd register. the pga gain can be either 2 or 4 determined by the pgag gain selection bit in the adcd register. the reference voltages of the adc integrator and comparator named vint and vcmp shown in the dual slope adc structure diagram can be selected by the adrr0 selection bit.
rev. 1.20 66 ?a? ?0? 201? rev. 1.20 67 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale
? ? ? ? ? ? ? ? ? ? ? ? -? ? ? -? ? ? ? ?? ?? ? ?
?

- ? ?
? ?

?
? ?
? ? ?
? ? ? ?? ? ? ?
?

?? ? ?
?

?
? ? ? ? ?

?
? ? ? ? ? dual slope adc structure an instrumentation amplifer is included to provide a high cmrr amplifying interface to differential signals from external sensors. with a standard instrumentation amplifer setup of three operational amplifiers and a dac for offset calibration, this structure provides a low noise sensor interface. two registers are used for overall control of the instrumentation amplifer and a single register for dac control. if these functions are not used they should be disabled using the register bits to reduce power consumption. op 3 + - op 4 - + 47u f 16v 0 . 1 u f 102 102 0 . 22 u f op 5 - + dchop op 5 p dopao op 5 n dopap dopan 105 82k v out bridge sensor gain = 1 / 2 / 4 / 8 / 16/ 32 gain = 4 / 5 / 6 / 7 / 8 / 9 ra _ string rb _ string 10k 10k 100pf 6 bits dac rsen rsen 100pf instrumentation amplifer
rev. 1.20 66 ?a? ?0? 201? rev. 1.20 67 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale dual slope a nolog digital convertor operation the following descriptions are based on the fact that the adrr0 bit is set to 0. the instrumentation amplifier and pga combination, form a differential input pre-amplifier which amplifies the sensor input signal. the combination of the integrator, the comparator, the resistor r ds , between dsrr and dsrc and the capacitor c ds , between dsrc and dscc, form the main body of the dual slope adc. the integrator integrates the output voltage increase or decrease and is controlled by the switch circuit - refer to the block diagram. the integration and de-integration curves are illustrated by the following. the comparator will switch the state from high to low when v c , which is the dscc pin voltage, drops to less than 1/6 vdso. in general applications, the application program will switch the adc to the charging mode for a fxed time called t i , which is the integrating time. it will then switch to the discharging mode and wait for v c to drop to less than 1/6 vdso. at this point the comparator will change state and store the time taken, t c , which is the de-integrating time. the following formula 1 can then be used to calculate the input voltage v a . formula 1: v a = (1/3) vdso (2 - t c /t i ). (based on adrr0=0) in user applications, it is required to choose the correct value of r ds and c ds to determine the t i value, to allow the v c value to operate between 5/6 vdso and 1/6 vdso. vfull cannot be greater than 5/6 vdso and v zero cannot be less than 1/6 vdso.
??
rev. 1.20 68 ?a? ?0? 201? rev. 1.20 69 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale adcr register bit 7 6 5 4 3 2 1 0 name adccken adint?1 adint?0 adc?po addisch1 addisch0 adpwren r/w r/w r/w r/w r r/w r/w r/w por 0 0 0 0 0 0 unknown bit 7 unimplemented, read as 0 bit 6 adccken : a/d convertor op chopper clock source on/off switching 0: disable 1: enable (clock value is defned by adcd register) bit 5~4 adintm1 , adintm0 : adcmpo data interrupt trigger mode defnition 00: no interrupt 01: rising edge 10: falling edge 11: both edge s bit 3 adcmpo : dual slope adc - last stage comparator output. read only bit, write data instructions will be ignored. during the discharging state, when the integrator output is less than the reference voltage,the adcmpo will change from high to low. bit 2~1 addisch1 ~ addisch0 : adc discharge/charge defnition 00: reserved 01: charging (integrator input connect to buffer output) 10: discharging (integrator input connect to vdso) 11: reserved bit 0 adpwren : dual slope block (including input op) power on/off switching 0: disable power 1: power source comes from the regulator adcd register bit 7 6 5 4 3 2 1 0 name pgag adis1 adis0 adrr0 adcd2 adcd1 adcd0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 1 1 bit 7 pgag : pga gain selection 0: gain = 2 1: gain = 4 bit 6~5 adis1 ~ adis0 : a/d pga input selection 00: from rfc pin 01: from th/lb pin 10: from dchop pin 11: reserved bit 4 adrr0 : a / d integrator and comparator reference voltage selection 0: (vint, vcmp) = (4/6 vdso, 1/6 vdso) 1: (vint, vcmp) = (4.4/6 vdso, 1/6 vdso) bit 3 unimplemented, read as 0
rev. 1.20 68 ?a? ?0? 201? rev. 1.20 69 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale bit 2~0 adcd2 ~ adcd 0 : c hopper clock defnition (adccken should be enable), the suggestion clock is around 10khz 000: (f sys /32)/1 001: (f sys /32)/2 010: (f sys /32)/4 011: (f sys /32)/8 100: (f sys /32)/16 101: (f sys /32)/32 110: (f sys /32)/64 111: (f sys /32)/128 iac0 register bit 7 6 5 4 3 2 1 0 name iaen g12 g11 g10 ia2en g02 g01 g00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 iaen : op3, op4 on/off control 0: off 1: on bit 6 ~ 4 g12~ g10 : instrumentation amplifer 2nd stage gain 000: 4 001: 5 010: 6 011: 7 100: 8 1xx: 9 bit 3 ia2en : op5 on/off control. 0: off 1: on bit 2 ~ 0 g02~ g00 : instrumentation amplifer 1st stage gain 000: 1 001: 2 010: 4 011: 8 100: 16 1xx: 32 iac1 register bit 7 6 5 4 3 2 1 0 name chopen bi_pga1 bi_pga0 iad2 iad1 iad0 rsen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 0 0 0 1 'x' unkno wn bit 7 chopen : op3, op4 chopper enable 0: disable 1: enable bit 6 ~ 5 bi_pga1~bi_pga0 : op3 and op4 operating current selection 00: i 01: 3i 10: 5i 11: 7i (op3 and op4 current=400a, ia (op3, op4, op5) current=1.2ma)
rev. 1.20 70 ?a? ?0? 201? rev. 1.20 71 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale bit 4 ~ 2 iad2~iad1 : chopper clock select ia chopper clock defned as: 000: clock= (f sys /32)/1 001: clock= (f sys /32)/2 010: clock= (f sys /32)/4 011: clock= (f sys /32)/8 100: clock= (f sys /32)/16 101: clock= (f sys /32)/32 110: clock= (f sys /32)/64 111: clock= (f sys /32)/128 a suggested clock speed has a range of around 8-10khz. note that chopen must be enabled C here the ia chopper clock is approximate 8k ~10k.(7.8125k ~ 11.71875k) and the adc chopper clock must be < 8k. bit 1 unimplemented, read as "0" bit 0 rsen : op5 external/internal gain setup control bit 0: open loop setup C gain defned by external reisistors. 1: closed loop setup C gain defned by g10, g11 and g12 bits in the iac0 register. iadac register bit 7 6 5 4 3 2 1 0 name iadaen d5 d4 d? d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 iadaen : ia dac enable/disable 0: disable 1: enable bit 6 unimplemented, read as "0" bit 5 ~ 0 d5~d0 : dac output voltage setup bits note: the dac output range is 0v ~ {v oreg -(v oreg /64)} 1 lsb = 1 digital code = v oreg /64 output voltage= v oreg /64*(d[5:0]) interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device provides an external interrupt and multiple internal interrupts . the external interrupt is controlled by the action of the external interrupt pin, while the internal interrupts are controlled by the timer/event counters , touch key and a/d converter. interrupt register overall interrupt control, which means interrupt enabling and request fag setting, is controlled by using three registers, intc0, intc1 and mfic. by controlling the appropriate enable bits in this registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request fag will be set by the microcontroller. the global enable fag if cleared to zero will disable all interrupts.
rev. 1.20 70 ?a? ?0? 201? rev. 1.20 71 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale intc0 register bit 7 6 5 4 3 2 1 0 name t1f t0f eif et1i et0i eei e?i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 t1f : timer/event counter 1 interrupt request fag 0: inactive 1: active bit 5 t0f : timer/event counter 0 interrupt request fag 0: inactive 1: active bit 4 eif : external interrupt request fag 0: inactive 1: active bit 3 et1i : timer/event counter 1 interrupt enable 0: disable 1: enable bit 2 et0i : timer/event counter 0 interrupt enable 0: disable 1: enable bit 1 eei : external interrupt enable 0: disable 1: enable bit 0 emi : master interrupt global enable 0: disable 1: enable intc 1 register bit 7 6 5 4 3 2 1 0 name tkf adf ?ff tke eadi e?fi r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 tkf : touch key interrupt request fag 0: inactive 1: active bit 5 adf : a / d c onvertor request fag 0: inactive 1: active bit 4 mff : multi - function interrupt request fag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 tke : touch key interrupt enable 0: disable 1: enable
rev. 1.20 72 ?a? ?0? 201? rev. 1.20 7? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale bit 1 eadi : a / d c onvertor interrupt enable 0: disable 1: enable bit 0 emfi : multi - function interrupt enable 0: disable 1: enable mfi c register bit 7 6 5 4 3 2 1 0 name ?16ctf ?10ctf t2f ?16cte ?10cte et2i r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 m16ct f : touch key module 16-bit counter interrupt request fag 0: inactive 1: active bit 5 m10ct f : touch key module 1 0 -bit counter interrupt request fag 0: inactive 1: active bit 4 t2 f : timer/event counter 2 interrupt request fag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 m16ct e : touch key module 16-bit counter interrupt enable 0: disable 1: enable bit 1 m10ct e : touch key module 1 0 -bit counter interrupt enable 0: disable 1: enable bit 0 e t2 i : timer/event counter 2 interrupt enable 0: disable 1: enable interrupt operation a timer/event or touch key counter overfow, an active edge on the external interrupt pin, a/d conversion completion , or a signal completion of the touch key sensor will all generate an interrupt request by setting their corresponding request fag, if their appropriate interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred.
rev. 1.20 72 ?a? ?0? 201? rev. 1.20 7? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale the various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority. 04 h 08 h 0ch 10 h 14 h 18 h low priority high reques t flag s enable bits master enable reques t flag s enable bits emi auto disabled in is r interrup t name interrup t name em i em i em i em i em i em i m16ctf tk 16-bit m16cte ei f int pi n ee i t0 f timer0 et0i t1 f timer1 et1i mf f multi-function emfi ad f a/ d ead i tk f touc h ke y tk e xx f request flag ? no auto reset in is r xx f request flag ? auto reset in is r xx e enable bi t m10ctf tk 10-bit m10cte t2 f timer2 et21 interrup t vector interrupts contained wi thin mult i- functi on interrupt 04 h 08 h 0ch 10 h 14 h 18 h low priority high reques t flag s enable bits master enable reques t flag s enable bits emi auto disabled in is r interrup t name interrup t name em i em i em i em i em i em i m16ctf tk 16-bit m16cte ei f int pi n ee i t0 f timer0 et0i t1 f timer1 et1i mf f multi-function emfi ad f a/ d ead i tk f touc h ke y tk e xx f request flag ? no auto reset in is r xx f request flag ? auto reset in is r xx e enable bi t m10ctf tk 10-bit m10cte t2 f timer2 et21 interrup t vector interrupts contained wi thin mult i- functi on interrupt interrupt structure once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. when an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps to the interrupt vector. if the device is in the sleep or idle mode and is woken up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector.
rev. 1.20 74 ?a? ?0? 201? rev. 1.20 75 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ?ain program enable bit set ? ?ain program automaticall? disable interrupt clear e?i & request flag wait for 2 ~ ? instruction c?cles isr entr? ... ... reti ( it will set e?i automaticall? ) interrupt request or interrupt flag set b? instruction n y interrupt flow interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 0 1 04h timer/event counter 0 overfow 2 08h timer/event counter 1 overfow ? 0ch ?ulti function interrupt (timer/event counter overfow 2 and touch key module 10-bit/16-bit counter overfow) 4 10h a / d c onvertor interrupt 5 14h touch ke ? interrupt 6 18h interrupt subroutine vector in cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced frst. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. external interrupt for an external interrupt to occur, the global interrupt enable bit, emi, and external interrupt enable bit, eei, must frst be set. an actual external interrupt will take place when the external interrupt request fag, eif, is set, a situation that will occur when an edge transition appears on the external int line. the type of transition that will trigger an external interrupt, whether high to low, low to high or both is determined by the eintc0 and eintc1 bits, which are bits 6 and 7 respectively, in the ctrl1 control register. these two bits can also disable the external interrupt function.
rev. 1.20 74 ?a? ?0? 201? rev. 1.20 75 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale eintc 1 eintc 0 edge trigger type 0 0 disable 0 1 falling edge trigger 1 0 rising edge trigger 1 1 dual edge trigger the external interrupt pin is pin-shared with the i/o pin pb4 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the intc0 register has been set and the edge trigger type has been selected using the ctrl1 register. the pin must also be setup as an input by setting the corresponding pbc.4 bit in the port control register. when the interrupt is enabled, the stack is not full and an active transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external interrupt request fag, eif, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, etni, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request fag, tnf, is set, a situation that will occur when the relevant timer/event counter overfows. when the interrupt is enabled, the stack is not full and a timer/event counter n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the timer interrupt request fag, tnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt the device has one multi-function interrupt. unlike the other independent interrupts, th i s interrupt have no independent source, but rather are formed from other existing interrupt sources, namely touch key 16-bit counter interrupt , touch key 10-bit counter interrupt and timer/event counter 2 interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flag mff is set. the multi-function interrupt flag will be set when any of its included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within multi-function interrupt will occur, a subroutine call to one of the multi- function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt flag will be automatically reset when the interrupt is serviced, the request fag from the original source of the multi-function interrupt, namely touch key 16-bit counter interrupt , touch key 10-bit counter interrupt and timer/event counter 2 interrupt will not be automatically reset and must be manually reset by the application program.
rev. 1.20 76 ?a? ?0? 201? rev. 1.20 77 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale a/d converter i nterrupt the a/d converter interrupt is initialized by setting the a/d converter request fag, caused by an end of a/d conversion. when the interrupt is enabled, the stack is not full and the adf is set, a sub- routine call will occur. the related interrupt request fag adf will be reset and the emi bit cleared to disable further interrupts. touch key interrupt the touch key interrupt is initiali z ed by setting the touch key interrupt request fag, tkf, bit 6 of intc1. this is caused by a signal completion of the touch key sensor. after the interrupt is enabled, and the stack is not full, and the tkf bit is set, a sub - routine call will occur. the related interrupt request fag tkf, will be reset and the emi bit is cleared to disable further interrupts. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is power down mode, the wake up being generated when the interrupt request flag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before entering the power down mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.20 76 ?a? ?0? 201? rev. 1.20 77 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale l cd driver for large volume applications, which incorporate an lcd in their design, the use of a custom display rather than a more expensive character based display reduces costs signifcantly. however, the corresponding signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper lcd operation to occur. the holtek lcd driver function, with its internal lcd signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom lcds. lcd memory an area of data memory is especially reserved for use by the lcd data. this data area is known as the lcd memory. any data written here will be automatically read by the internal lcd driver circuits, which will in turn automatically generate the necessary lcd driving signals. therefore any data written into the lcd memory will be immediately refected into the actual lcd display connected to the microcontroller. the start address of the lcd memory is 40h; the end address of the lcd memory is 5bh. as the lcd data memory addresses overlap those of the general purpose data memory, the lcd data memory is stored in its own memory data bank, which is different from that of the general purpose data memory. the lcd data memory is stored in bank 1. the data memory bank is chosen by using the bank pointer, which is a special function register in the data memory, with the name, bp. when the lowest bit of the bank pointer has the binary value 0, only the general purpose data memory will be accessed, no read or write actions to the lcd memory will take place. to access the lcd memory therefore requires frst that bank 1 is selected by setting the lowest bit of the bank pointer to the binary value 1. after this, the lcd memory can then be accessed by using indirect addressing through the use of memory pointer mp1. with bank 1 selected, then using mp1 to read or write to the memory area 40h~ 5b h, will result in operations to the lcd memory. directly addressing the lcd memory is not applicable and will result in a data access to the bank 0 general purpose data memory. lcd memory map
rev. 1.20 78 ?a? ?0? 201? rev. 1.20 79 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale lcd registers a single lcd control register s in the data memory, known as lcdc, is used to control the various setup features of the lcd driver. various bits in this register control functions such as va voltage, bias type, duty type as well as lcd com/seg selection . lcdc register bit 7 6 5 4 3 2 1 0 name lcdpd vas rcs css2 css1 css0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 lcdpd : lcd on/off control 0: lcd enable 1: lcd disable bit 6 va s : va voltage selection for c type lcd 0: voreg 1: 1.5voreg bit 5 unimplemented, read as 0 bit 4 rcs : lcd type r or c 0: r type 1: c type bit 3 unimplemented, read as 0 bit 2~0 css2~css0 : lcd com[7:4]/seg[27:24] selection, re fer to the following table for details note: when the charge pump output voltage is equal to vdd , the c-type lcd bias can only be select ed as va=voreg . when the charge pump output voltage is equal to 2vdd , the c-type lcd bias can be select ed as va=voreg or va=voreg1.5 . when the c-type lcd voltage is selected to be pumped to voregx1.5 , the power supply to vdd should be limited to 2.6v~5.5v . ccs[2:0] duty com4/seg27 com5/seg26 com6/seg25 com7/seg24 segcom (maximum) 000 1/4 seg27 seg26 seg25 seg24 284 001 1/5 co?4 seg26 seg25 seg24 275 010 1/6 co?4 co?5 seg25 seg24 266 011 1/7 co?4 co?5 co?6 seg24 257 1 1/8 co?4 co?5 co?6 co?7 248 the lcdout register is used to determine if the output function of lcd pins seg0~seg 7 are used a lcd segment drivers or normal i/o operation .
rev. 1.20 78 ?a? ?0? 201? rev. 1.20 79 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale lcdout register bit 7 6 5 4 3 2 1 0 name lcds7 lcds6 lcds5 lcds4 lcds? lcds2 lcds1 lcds0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 lcds7 : select seg7 or i/o 0: i/o 1: seg7 bit 6 lcds 6 : select seg 6 or i/o 0: i/o 1: seg 6 bit 5 lcds 5 : select seg 5 or i/o 0: i/o 1: seg 5 bit 4 lcds 4 : select seg 4 or i/o 0: i/o 1: seg 4 bit 3 lcds 3 : select seg 3 or i/o 0: i/o 1: seg 3 bit 2 lcds 2 : select seg 2 or i/o 0: i/o 1: seg 2 bit 1 lcds 1 : select seg 1 or i/o 0: i/o 1: seg 1 bit 0 lcds 0 : select seg 0 or i/o 0: i/o 1: seg 0 lcd clock the lcd clock is driven by the f sub clock, which then passes through a divider, the division ratio of which is selected by the lcd clock selection bits, lcdck1 and lcdck0, in the ctrl0 register to provide a lcd clock frequency of f sub /3, f sub /4 or f sub /8. the lcd clock source f sub can be derived from the lirc or lxt oscillator selected by the selection bit, named fsubs. note that the f sub clock can be enabled or disabled in the power down mode by the f sub clock control bit fsubc in the ctrl0 register. lcd driver output the output structure of the device lcd driver can be 248 to 284. the lcd driver bias type has r and c type. the c/r type and number of com and seg is selected by software option. the lcd driver has a fxed 1/3 bias . the nature of liquid crystal displays require that only ac voltages can be applied to their pixels as the application of dc voltages to lcd pixels may cause permanent damage. for this reason the relative contrast of an lcd display is controlled by the actual rms voltage applied to each pixel, which is equal to the rms value of the voltage on the com pin minus the voltage applied to the seg pin. this differential rms voltage must be greater than the lcd saturation voltage
rev. 1.20 80 ?a? ?0? 201? rev. 1.20 81 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale for the pixel to be on and less than the threshold voltage for the pixel to be off. the requirement to limit the dc voltage to zero and to control as many pixels as possible with a minimum number of connections, requires that both a time and amplitude signal is generated and applied to the application lcd. these time and amplitude varying signals are automatically generated by the lcd driver circuits in the microcontroller. what is known as the duty determines the number of common lines used, which are also known as backplanes or coms. the duty, which is chosen by control bit s to have a value of 1/4 , 1/5, 1/6 or 1/7, 1/8 and which equates to a com number of 3 , 4, 5, 6 and 7 respectively, therefore defnes the number of time divisions within each lcd signal frame. the accompanying timing diagrams depict the lcd signals generated by the microcontroller for various values of duty and bias. lcd voltage source and biasing the time and amplitude varying signals generated by the lcd driver function require the generation of several voltage levels for their operation. the number of voltage levels used by the signal depends upon the value of the cssn bit s in the lcdc register. the device can have either r type or c type biasing selected via the rcs bit in the lcdc register. selecting the c type biasing will enable an internal charge pump whose multiplying ration can be selected using an additional confguration option. for r type biasing an external lcd voltage source is supplied by the internal vlcd biasing voltage. this could be the microcontroller power supply or some other voltage source. for the r type 1/ 3 bias selection, three voltage levels vss, va , vb and vc are utilised. the voltage va is equal to vlcd. vb is equal to 2 / 3 vlcd. v c is equal to 1 / 3 vlcd . note that no external capacitors or resistors are required to be connected if r type biasing is used. for c type biasing an external lcd voltage source also is supplied by the internal vlcd biasing voltage or vmax . the c type biasing scheme uses an internal charge pump circuit, which in the case of the 1/3 bias can generate voltages higher than what is supplied by vlcd. this feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the lcd. the bit vas is selected for va voltage in c type lcd. the relation of lcd voltage is as following fgure.
? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? -? -? ? -? ? -? ? -? ? -? ? -? ? note: 1. 1/3bias, vas= 1, vab is va. 2. 1/3bias, vas= 0, vab is vb.
rev. 1.20 80 ?a? ?0? 201? rev. 1.20 81 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale

? ? ? ? ?
?
?
?
?
?
programming considerations certain precautions must be taken when programming the lcd. one of these is to ensure that the lcd memory is properly initialised after the microcontroller is powered on. like the general purpose data memory, the contents of the lcd memory are in an unknown condition after power- on. as the contents of the lcd memory will be mapped into the actual lcd, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. consideration must also be given to the capacitive load of the actual lcd used in the application. as the load presented to the microcontroller by lcd pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the com lines which may be connected to many lcd pixels. the accompanying diagram depicts the equivalent circuit of the lcd. with such a frequency chosen, the microcontroller internal lcd driver circuits will ensure that the appropriate lcd driving signals are generated to obtain a suitable lcd frame frequency.
rev. 1.20 82 ?a? ?0? 201? rev. 1.20 8? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale confguration options confguration options refer to certain options within the mcu that are programmed into the otp program memory device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 s?stem oscillator selection - f sys : 1. hxt 2. erc ?. hirc 2 hirc frequenc? selection: 1. 4?hz 2. 8?hz ? . 12?hz ? external ?2khz oscillator selection: 1. i/o 2. ?2.768khz external cr?stal 4 s? stem oscillator sst period selection: 1.1024 clocks 2.2 clocks reset pin options 5 p a7 /res pin options: 1. res pin 2. i/o pin lcd options 6 lcd function in power down mode: 1. enable 2. disable 7 r t?pe drive current selection: 1. 50 a 2. 100 a watchdog options 8 wdt function 1. alwa? s enable 2. wdt enable/disable b ? s/w 9 wdt clock selection - f s : 1. internal 12khz rc oscillator - lirc 2. f sys /4 ?. ?2.768khz oscillator 10 clrwdt instruction selection: 1. instruction 2. instruction
rev. 1.20 82 ?a? ?0? 201? rev. 1.20 8? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale body fat measurement function the body fat circuit consists of a sine wave generator, an amplifer and a flter. the circuit has been designed for maximum fexibility and has a high degree of functional integration to implement a body fat measurement function . sine wave generator the sine wave generator consists of a frequency divider, counter, ram, 10-bit dac and op0. the circuit can generate a sine wave output with a frequency range of 5khz~50khz using a 329 bit ram for the sine wave pattern simulation. the frequency divider will multiply by dn/m to generate a clock for the counter. the following points must be noted to understand how the sine wave is generated: system clock/m = sine wave frequency system clock (dn/m) = the count rate of the counter m must be a multiple of n and 8. m = n dn dnr = dn/2 dn: sine wave cycle data numerical value (dn <= 64) dnr: the data numerical value of the 1/2 sine wave cycle stored in ram (dnr <= 32) refer to the following table and fgure for more details. system frequency 4?hz 8?hz 12?hz s ine w ave frequency (khz) 50 5 50 5 50 5 m 80 800 160 1600 240 2400 n 2 16 4 25 4 40 dn 40 50 40 64 60 60 dnr 20 25 20 ?2 ?0 ?0 p0 p1 p2 - 512 511 0 p dnr- 1 p dnr -2 . . . p dnr -3
rev. 1.20 84 ?a? ?0? 201? rev. 1.20 85 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale only a half sine wave pattern p0~p dnr-1 is generated which is stored in ram bank 2 with an address range of 40h~7fh. t he sine wave pattern data bits [7:0] are stored with even address es while the sine wave pattern data bit [8] is stored with an odd address. once the sine wave generator is enabled, the cpu will not be able to write or read data to/from this ram area. the sine generator will read the ram data and transmit it to the 10-bit dac. the device will read the half sine wave pattern from the ram and generate the actual sine waveform on the sin pin. r efer to the following diagram: 2's complement d[9:0] d[9] dn_cnt/2 >= dnr 0 1 0 1 + sine[8:0] dac 0 1 d[8:0] 40h 41h 42h 43h 7dh 7ch 7bh 7eh 7fh . . . ram(bank 2) sine0[8:0] sine1[8:0] sine2[8:0] sine3[8:0] . . . . . sine30[8:0] sine31[8:0] sine32[8:0] sine33[8:0] sine wave pattern sine0[7:0] sine0[8] sine1[7:0] sine1[8] sine30[7:0] sine30[ 8] sine31[7:0] sine31[ 8]
rev. 1.20 84 ?a? ?0? 201? rev. 1.20 85 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale s gc register bit 7 6 5 4 3 2 1 0 name sgen bren r/w r/w r/w por 0 0 0 0 0 0 bit 7 sgen : sine generator enable bit 0: disable 1: enable w hen this bit is equal to 0, the op0 and 10-bit dac will be in a power down mode . bit 6~5 unimplemented, read as 0 bit 4 bren : bias resistor enable 0: disable - power down mode 1: enable - normal mode when this bit is enabled, it will generate a 0.5voreg voltage for the non-inverting input of opa1 and opa2. bit 3~0 unimplemented, read as 0 s gn register bit 7 6 5 4 3 2 1 0 name d5 d4 d? d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 d5~d0 : system frequency multiplicator - n multiplicator (n) equal to d [5:0] + 1 s gdnr register bit 7 6 5 4 3 2 1 0 name d4 d? d2 d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4~0 d4~d0 : 1/2 sine wave cycle numerical value stored in ram bank 2 dnr is equal to d [4:0] + 1 amplifer the amplifer consists of op1, op2, a 6-bit dac and analog switc hes. op2 is a differential amplifer with 1~5 multiple gain. the 6-bit dac offers a reference voltage to the non-inverting input of op2. the user can turn on and off switch 0 to 7 to obtain a reference resistor voltage and a body resistor voltage. the body and reference impedance can be obtained by using the sw0 ~ sw7 switches. refer to following table for this impedance switching. switch sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 foot impedance o o o reference 1k o o o reference 200 o o o o: s witch closed.
rev. 1.20 86 ?a? ?0? 201? rev. 1.20 87 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale opac register bit 7 6 5 4 3 2 1 0 name opa en op2g? op2g2 op2g1 op2g0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 opa en : amplifer enable control 0: enable 1: disable when this bit is equal to 1, op1, op2 and the 6-bit dac will be in a power down mode. bit 6~4 unimplemented, read as 0 bit 3~0 op2g3 ~ op2g 0 : op2 gain control 0001: 1.14 0010: 1. 31 0011: 1. 5 0100: 1. 73 0101: 2 0110: 2.33 0111: 2.75 1000: 3.285 1001: 4 1010: 5 others : 1 swc register bit 7 6 5 4 3 2 1 0 name sw7 sw6 sw5 sw4 sw? sw2 sw1 sw0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 sw7 : s witch 7 control bit 0: open 1: short bit 6 sw6 : s witch 6 control bit 0: open 1: short bit 5 sw5 : s witch 5 control bit 0: open 1: short bit 4 sw4 : s witch 4 control bit 0: open 1: short bit 3 sw3 : s witch 3 control bit 0: open 1: short bit 2 sw2 : s witch 2 control bit 0: open 1: short bit 1 sw1 : s witch 1 control bit 0: open 1: short bit 0 sw0 : s witch 0 control bit 0: open 1: short
rev. 1.20 86 ?a? ?0? 201? rev. 1.20 87 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale daco register bit 7 6 5 4 3 2 1 0 name d5 d4 d? d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 d5~d0 : 6-bit dac output voltage output voltage = 0.5v oreg * ((d[5:0] + 1)/64) filter the flter consists of cp0, a pmos transistor and some analog switch e s. the flter contains a peak detection function for which an external capacit or will store the peak value for transmission to the adc. switches sw8 and sw9 are for capacit or discharge purposes. ftrc register bit 7 6 5 4 3 2 1 0 name ftr en sw9 sw8 r/w r/w r/w r/w por 0 0 0 bit 7 ftr en : flter enable 0: disable 1: enable when this bit is equal to 0, cp0 and the pmos transistor will be in a power down mode. bit 6~5 unimplemented, read as 0 bit 4 reserved C must be cleared to 0 bit 3~2 unimplemented, read as 0 bit 1 sw9 : s witch 9 control bit 0: open 1: short bit 0 sw8 : s witch 8 control bit 0: open 1: short
rev. 1.20 88 ?a? ?0? 201? rev. 1.20 89 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale application circuits ????????? ????????? ????? ????? ????? ????? ???? ???? ???? ????? ??????? ??????? ??????? ??????? ??????? ?????? ??????? ???????? ???????? ???????? ???????? ???????? ??? ??? ???? ???? ??? ? ??? ??? ?????????? ?? ????? ????? ????? ????? ????? ?? ?? ?? ???? ??? ??? ???? ? ??? ???????? ?? ?? ? ?? ?? ???????? ??????????????????? ????????????????????????? ???????????????? ????????? ???? ?? ????? ??????? ???????? ?? ???? ???? ???? ???? ???? ?? ? ????? ????? ????? ????? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? ??? ?? ??? ??? ?????
rev. 1.20 88 ?a? ?0? 201? rev. 1.20 89 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different
rev. 1.20 90 ?a? ?0? 201? rev. 1.20 91 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "halt" instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.20 90 ?a? ?0? 201? rev. 1.20 91 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[m] add data ?emor? to acc 1 z? c? ac? ov add? a?[m] add acc to data ?emor? 1 note z? c? ac? ov add a?x add immediate data to acc 1 z? c? ac? ov adc a?[m] add data ?emor? to acc with carr? 1 z? c? ac? ov adc? a?[m] add acc to data memor ? with carr? 1 note z? c? ac? ov sub a?x subtract immediate data from the acc 1 z? c? ac? ov sub a?[m] subtract data ?emor? from acc 1 z? c? ac? ov sub? a?[m] subtract data ?emor? from acc with result in data ?emor? 1 note z? c? ac? ov sbc a?[m] subtract data ?emor? from acc with carr? 1 z? c? ac? ov sbc? a?[m] subtract data ?emor? from acc with carr ?? result in data ?emor? 1 note z? c? ac? ov daa [m] decimal adjust acc for addition with result in data ?emor? 1 note c logic operation and a?[m] logical and data ?emor? to acc 1 z or a?[m] logical or data ?emor? to acc 1 z xor a?[m] logical xor data ?emor? to acc 1 z and? a?[m] logical and acc to data ?emor? 1 note z or? a?[m] logical or acc to data ?emor? 1 note z xor? a?[m] logical xor acc to data ?emor? 1 note z and a?x logical and immediate data to acc 1 z or a?x logical or immediate data to acc 1 z xor a?x logical xor immediate data to acc 1 z cpl [m] complement data ?emor? 1 note z cpla [m] complement data ?emor? with result in acc 1 z increment & decrement inca [m] increment data ?emor? with result in acc 1 z inc [m] increment data ?emor? 1 note z deca [m] decrement data ?emor? with result in acc 1 z dec [m] decrement data ?emor? 1 note z rotate rra [m] rotate data ?emor? right with result in acc 1 none rr [m] rotate data ?emor? right 1 note none rrca [m] rotate data ?emor? right through carr? with result in acc 1 c rrc [m] rotate data ?emor? right through carr? 1 note c rla [m] rotate data ?emor? left with result in acc 1 none rl [m] rotate data ?emor? left 1 note none rlca [m] rotate data ?emor? left through carr? with result in acc 1 c rlc [m] rotate data ?emor? left through carr? 1 note c
rev. 1.20 92 ?a? ?0? 201? rev. 1.20 9? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale mnemonic description cycles flag affected data move ? ov a?[m] ?ove data ?emor? to acc 1 none ?ov [m]?a ? ove acc to data ?emor? 1 note none ? ov a?x ? ove immediate data to acc 1 none bit operation clr [m].i clear bit of data ?emor? 1 note none set [m].i set bit of data ?emor? 1 note none branch j? p addr jump unconditionall? 2 none sz [m] skip if data ?emor? is zero 1 note none sza [m] skip if data ?emor? is zero with data movement to acc 1 note none sz [m].i skip if bit i of data ?emor? is zero 1 note none snz [m].i skip if bit i of data ?emor? is not zero 1 note none siz [m] skip if increment data ?emor? is zero 1 note none sdz [m] skip if decrement data ?emor? is zero 1 note none siza [m] skip if increment data ?emor? is zero with result in acc 1 note none sdza [m] skip if decrement data ?emor? is zero with result in acc 1 note none call addr subroutine call 2 none ret return from subroutine 2 none ret a ?x return from subroutine and load immediate data to acc 2 none reti return from interrupt 2 none table read tabrdc [m] read table (current page) to tblh and data ?emor? 2 note none tabrdl [m] read table (last page) to tblh and data ?emor? 2 note none miscellaneous nop no operation 1 none clr [m] clear data ?emor? 1 note none set [m] set data ?emor? 1 note none clr wdt clear watchdog timer 1 to ? pdf clr wdt1 pre-clear watchdog timer 1 to ? pdf clr wdt2 pre-clear watchdog timer 1 to ? pdf swap [m] swap nibbles of data ?emor? 1 note none swapa [m] swap nibbles of data ?emor? with result in acc 1 none halt enter power down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf fags may be affected by the execution status. the to and pdf fags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
rev. 1.20 92 ?a? ?0? 201? rev. 1.20 9? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale instruction defnition add data ?emor? to acc with carr? the contents of the specified data ?emor ?? accumulator and the carr? flag are added. the result is stored in the accumulator. acc acc + [m] + c ov ? z? ac? c add acc to data ?emor? with carr? the contents of the specified data ?emor ?? accumulator and the carr? flag are added. the result is stored in the specifed data memory. [m] acc + [m] + c ov ? z? ac? c add data ?emor? to acc the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. acc acc + [m] ov ? z? ac? c add immediate data to acc the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. ac acc + x ov ? z? ac? c add acc to data ?emor? the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. [m] acc + [m] ov ? z? ac? c logical and data ?emor? to acc data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. acc acc " and " [m] z logical and immediate data to acc data in the accumulator and the specifed immediate data perform a bitwise logical and operation. the result is stored in the accumulator. acc acc " and " x z logical and acc to data ?emor? data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data ?emor? . [m] acc " and " [m] z adc a,[m] description operation affected fag(s) adcm a,[m] description operation affected fag(s) add a,[m] description operation affected fag(s) add a,x description operation affected fag(s) addm a,[m] description operation affected fag(s) and a,[m] description operation affected fag(s) and a,x description operation affected fag(s) andm a,[m] description operation affected fag(s)
rev. 1.20 94 ?a? ?0? 201? rev. 1.20 95 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale subroutine call unconditionally calls a subroutine at the specifed address. the program counter then increments b ? 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation? it is a two c?cle instruction. stack program counter + 1 program counter addr none clear data ?emor? each bit of the specifed data memory is cleared to 0. [m] 00h none clear bit of data ?emor? bit i of the specifed data memory is cleared to 0. [m].i 0 none clear watchdog timer the to, pdf fags and the wdt are all cleared. wdt cleared to 0 pdf 0 to ? pdf pre-clear watchdog timer the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternatel ? with clr wdt2 to have effect. repetitivel ? executing this instruction without alternatel? executing clr wdt2 will have no effect. wdt cleared to 0 pdf 0 to ? pdf pre-clear watchdog timer the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternatel ? with clr wdt1 to have effect. repetitivel ? executing this instruction without alternatel? executing wdt cleared to 0 pdf 0 to ? pdf call addr description operation affected fag(s) clr [m] description operation affected fag(s) clr [m].i description operation affected fag(s) clr wdt description operation affected fag(s) clr wdt1 description operation affected fag(s) clr wdt2 description operation affected fag(s)
rev. 1.20 94 ?a? ?0? 201? rev. 1.20 95 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale complement data ?emor? each bit of the specifed data memory is logically complemented (1 ' s complement). bits which previousl? contained a 1 are changed to 0 and vice versa. [m] [m] z complement data ?emor? with result in acc each bit of the specified data ?emor? is logicall? complemented (1 ' s complement). bits which previousl? contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data ?emor? remain unchanged. acc [m] z decimal-adjust acc for addition with result in data ?emor? convert the contents of the accumulator value to a bcd ( binar ? coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed b? adding 00h? 06h? 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100 ? it allows multiple precision decimal addition. [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h c decrement data ?emor? data in the specifed data memory is decremented by 1. [m] [m] C 1 z decrement data ?emor? with result in acc data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data ?emor? remain unchanged. acc [m] C 1 z cpl [m] description operation affected fag(s) cpla [m] description operation affected fag(s) daa [m] description operation affected fag(s) dec [m] description operation affected fag(s) deca [m] description operation affected fag(s)
rev. 1.20 96 ?a? ?0? 201? rev. 1.20 97 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale enter power down mode this instruction stops the program execution and turns off the s ? stem clock. the contents of the data ?emor? and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. to 0 pdf 0 to ? pdf increment data ?emor? data in the specifed data memory is incremented by 1. [m] [m]+1 z increment data ?emor? with result in acc data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data ?emor? remain unchanged. acc [m]+1 z jump unconditionall? the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dumm ? instruction while the new address is loaded? it is a two c?cle instruction. program counter addr none ?ove data ?emor? to acc the contents of the specifed data memory are copied to the accumulator. acc [m] none ? ove immediate data to acc the immediate data specifed is loaded into the accumulator. acc x none ? ove acc to data ?emor? the contents of the accumulator are copied to the specifed data memory. [m] acc none no operation no operation is performed. execution continues with the next instruction. no operation none halt description operation affected fag(s) inc [m] description operation affected fag(s) inca [m] description operation affected fag(s) jmp addr description operation affected fag(s) mov a,[m] description operation affected fag(s) mov a,x description operation affected fag(s) mov [m],a description operation affected fag(s) nop description operation affected fag(s)
rev. 1.20 96 ?a? ?0? 201? rev. 1.20 97 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale logical or data ?emor? to acc data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. acc acc " or " [m] z logical or immediate data to acc data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. acc acc " or " x z logical or acc to data ?emor? data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data ?emor? . [m] acc " or " [m] z return from subroutine the program counter is restored from the stack. program execution continues at the restored address. program counter stack none return from subroutine and load immediate data to acc the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. program counter stack acc x none return from interrupt the program counter is restored from the stack and the interrupts are re-enabled b? setting the e?i bit. e? i is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed? the pending interrupt routine will be processed before returning to the main program. program counter stack e?i 1 none rotate data ?emor? left the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 none or a,[m] description operation affected fag(s) or a,x description operation affected fag(s) orm a,[m] description operation affected fag(s) ret description operation affected fag(s) ret a,x description operation affected fag(s) reti description operation affected fag(s) rl [m] description operation affected fag(s)
rev. 1.20 98 ?a? ?0? 201? rev. 1.20 99 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale rotate data ?emor? left with result in acc the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data ?emor? remain unchanged. acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 none rotate data ?emor? left through carr? the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 c rotate data ?emor? left through carr? with result in acc data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data ?emor? remain unchanged. acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 c rotate data ?emor? right the contents of the specified data ?emor? are rotated right b? 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 none rotate data ?emor? right with result in acc data in the specified data ?emor? and the carr? flag are rotated right b? 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data ?emor? remain unchanged. acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 none rotate data ?emor? right through carr? the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 c rla [m] description operation affected fag(s) rlc [m] description operation affected fag(s) rlca [m] description operation affected fag(s) rr [m] description operation affected fag(s) rra [m] description operation affected fag(s) rrc [m] description operation affected fag(s)
rev. 1.20 98 ?a? ?0? 201? rev. 1.20 99 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale rotate data ?emor? right through carr? with result in acc data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data ?emor? remain unchanged. acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 c subtract data ?emor? from acc with carr? the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc C [m] C c ov ? z? ac? c subtract data ?emor? from acc with carr? and result in data ?emor? the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data ?emor? . note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc C [m] C c ov ? z? ac? c skip if decrement data ?emor? is 0 the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dumm ? instruction while the next instruction is fetched ? it is a two c? cle instruction. if the result is not 0 the program proceeds with the following instruction. [m] [m] C 1 skip if [m] = 0 none skip if decrement data ?emor? is zero with result in acc the contents of the specifed data memory are frst decremented by 1. if the result is 0? the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dumm ? instruction while the next instruction is fetched? it is a two c? cle instruction. if the result is not 0? the program proceeds with the following instruction. acc [m] C 1 skip if acc = 0 none rrca [m] description operation affected fag(s) sbc a,[m] description operation affected fag(s) sbcm a,[m] description operation affected fag(s) sdz [m] description operation affected fag(s) sdza [m] description operation affected fag(s)
rev. 1.20 100 ?a? ?0? 201? rev. 1.20 101 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale set data ?emor? each bit of the specifed data memory is set to 1. [m] ffh none set bit of data ?emor? bit i of the specifed data memory is set to 1. [m].1 1 none skip if increment data ?emor? is 0 the contents of the specifed data memory are frst incremented by 1. if the result is 0? the following instruction is skipped. as this requires the insertion of a dumm? instruction while the next instruction is fetched ? it is a two c? cle instruction. if the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 skip if [m] = 0 none skip if increment data ?emor? is zero with result in acc the contents of the specifed data memory are frst incremented by 1. if the result is 0? the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dumm ? instruction while the next instruction is fetched? it is a two c? cle instruction. if the result is not 0 the program proceeds with the following instruction. acc [m] + 1 skip if acc = 0 none skip if bit i of data ?emor? is not 0 if bit i of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dumm ? instruction while the next instruction is fetched? it is a two c? cle instruction. if the result is 0 the program proceeds with the following instruction. skip if [m].i 0 none subtract data ?emor? from acc the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative ? the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc C [m] ov ? z? ac? c set [m] description operation affected fag(s) set [m].i description operation affected fag(s) siz [m] description operation affected fag(s) siza [m] description operation affected fag(s) snz [m].i description operation affected fag(s) sub a,[m] description operation affected fag(s)
rev. 1.20 100 ?a? ?0? 201? rev. 1.20 101 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale subtract data ?emor? from acc with result in data ?emor? the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data ?emor? . note that if the result of subtraction is negative? the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. [m] acc C [m] ov ? z? ac? c subtract immediate data from acc the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative? the c flag will be cleared to 0? otherwise if the result is positive or zero, the c fag will be set to 1. acc acc C x ov ? z? ac? c swap nibbles of data ?emor? the low-order and high-order nibbles of the specified data ?emor? are interchanged. [m].3~[m].0?[m].7 ~ [m].4 none swap nibbles of data ?emor? with result in acc the low-order and high-order nibbles of the specified data ?emor? are interchanged. the result is stored in the accumulator. the contents of the data ?emor? remain unchanged. acc.? ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].? ~ [m].0 none skip if data ?emor? is 0 if the contents of the specified data ?emor? is 0? the following instruction is skipped. as this requires the insertion of a dumm ? instruction while the next instruction is fetched? it is a two c? cle instruction. if the result is not 0 the program proceeds with the following instruction. skip if [m] = 0 none skip if data ?emor? is 0 with data movement to acc the contents of the specifed data memory are copied to the accumulator. if the value is zero? the following instruction is skipped. as this requires the insertion of a dumm? instruction while the next instruction is fetched? it is a two c?cle instruction. if the result is not 0 the program proceeds with the following instruction. acc [m] skip if [m] = 0 none subm a,[m] description operation affected fag(s) sub a,x description operation affected fag(s) swap [m] description operation affected fag(s) swapa [m] description operation affected fag(s) sz [m] description operation affected fag(s) sza [m] description operation affected fag(s)
rev. 1.20 102 ?a? ?0? 201? rev. 1.20 10? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale skip if bit i of data ?emor? is 0 if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dumm ? instruction while the next instruction is fetched? it is a two c ? cle instruction. if the result is not 0? the program proceeds with the following instruction. skip if [m].i = 0 none read table (current page) to tblh and data ?emor? the low b ? te of the program code (current page) addressed b? the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] program code (low b?te) tblh program code (high b?te) none read table (last page) to tblh and data ?emor? the low b?te of the program code (last page) addressed b? the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] program code (low b?te) tblh program code (high b?te) none logical xor data ?emor? to acc data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. acc acc " xor " [m] z logical xor acc to data ?emor? data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data ?emor? . [m] acc " xor " [m] z logical xor immediate data to acc data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. acc acc " xor " x z sz [m].i description operation affected fag(s) tabrdc [m] description operation affected fag(s) tabrdl [m] description operation affected fag(s) xor a,[m] description operation affected fag(s) xorm a,[m] description operation affected fag(s) xor a,x description operation affected fag(s)
rev. 1.20 102 ?a? ?0? 201? rev. 1.20 10? ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. further package information (include outline dimensions, product tape and reel specifcations) packing meterials information carton information pb free products green packages products
rev. 1.20 104 ?a? ?0? 201? rev. 1.20 105 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale 80-pin lqfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.469 D 0.476 b 0.?90 D 0.?98 c 0.469 D 0.476 d 0.?90 D 0.?98 e D 0.016 D f D 0.006 D g 0.05? D 0.057 h D D 0.06? i D 0.004 D j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 11.90 D 12.10 b 9.90 D 10.10 c 11.90 D 12.10 d 9.90 D 10.10 e D 0.40 D f D 0.16 D g 1.?5 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7
rev. 1.20 104 ?a? ?0? 201? rev. 1.20 105 ?a? ?0? 201? ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale ht45r2k-c/-b/-a dual slope 16k/8k/4k assp mcu for body fat scale cop?right ? 201? b? holtek se? iconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however ? holtek assumes no responsibilit? arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warrant ? or representation that such applications will be suitable without further modification ? nor recommends the use of its products for application that ma? present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or s ? stems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

▲Up To Search▲

Price & Availability of HT45R2K-A

	To Download HT45R2K-A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .